-#!/usr/bin/env python
-from nmigen import Platform # Not sure where platform comes from?
+#!/usr/bin/env python3
+from nmigen.build.dsl import Resource, Subsignal, Pins
+from nmigen.build.plat import TemplatedPlatform
+from nmigen import Elaboratable, Signal, Module
# Was thinking of using these functions, but skipped for simplicity for now
-#from pinfunctions import i2s, lpc, emmc, sdmmc, mspi, mquadspi, spi, quadspi, i2c, mi2c, jtag, uart, uartfull, rgbttl, ulpi, rgmii, flexbus1, flexbus2, sdram1, sdram2, sdram3, vss, vdd, sys, eint, pwm, gpio
+# XXX nope. the output from JSON file.
+#from pinfunctions import (i2s, lpc, emmc, sdmmc, mspi, mquadspi, spi,
+# quadspi, i2c, mi2c, jtag, uart, uartfull, rgbttl, ulpi, rgmii, flexbus1,
+# flexbus2, sdram1, sdram2, sdram3, vss, vdd, sys, eint, pwm, gpio)
+
+# File for stage 1 pinmux tested proposed by Luke,
+https://bugs.libre-soc.org/show_bug.cgi?id=50#c10
-# File for stage 1 pinmux tested proposed by Luke, https://bugs.libre-soc.org/show_bug.cgi?id=50#c10
def dummy_pinset():
# sigh this needs to come from pinmux.
- num_gpios = 16
- num_eint = 3
- num_pow3v3 = 10
- num_pow1v8 = 13
-
gpios = []
- for i in range(num_gpios):
+ for i in range(16):
gpios.append("%d*" % i)
-
- eint = []
- for i in range(num_eint):
- eint.append("%d-" % i)
-
- vdd3v3 = []
- vss3v3 = []
- vdd1v8 = []
- vss1v8 = []
- for i in range(num_pow3v3):
- vdd3v3.append("%d-" % i)
- vss3v3.append("%d-" % i)
- for i in range(num_pow1v8):
- vdd1v8.append("%d-" % i)
- vss1v8.append("%d-" % i)
-
- rgmii = ['erxd0-', 'erxd1-', 'erxd2-', 'erxd3-', 'etxd0+', 'etxd1+', 'etxd2+', 'etxd3+', 'erxck-', 'erxerr-', 'erxdv-', 'emdc+', 'emdio*', 'etxen+', 'etxck+', 'ecrs-', 'ecol+', 'etxerr+']
- ulpi = ['CK+', 'DIR+', 'STP+', 'NXT+', 'D0*', 'D1*', 'D2*', 'D3*', 'D4*', 'D5*', 'D6*', 'D7*']
-
- sdr = ['DQM0+', 'D0*', 'D1*', 'D2*', 'D3*', 'D4*', 'D5*', 'D6*', 'D7*', 'BA0+', 'BA1+', 'AD0+', 'AD1+', 'AD2+', 'AD3+', 'AD4+', 'AD5+', 'AD6+', 'AD7+', 'AD8+', 'AD9+', 'CLK+', 'CKE+', 'RASn+', 'CASn+', 'WEn+', 'CSn0+']
return {'uart': ['tx+', 'rx-'],
'gpio': gpios,
- 'i2c': ['sda*', 'scl+'],
- 'rg0': rgmii,
- 'rg1': rgmii,
- 'rg2': rgmii,
- 'rg3': rgmii,
- 'rg4': rgmii,
- 'ulpi0': ulpi,
- 'ulpi1': ulpi,
- 'sdr': sdr,
- 'jtag': ['TMS-', 'TDI-', 'TDO+', 'TCK+'],
- 'vdd3v3': vdd3v3,
- 'vss3v3': vss3v3,
- 'vdd1v8': vdd1v8,
- 'vss1v8': vss1v8,
- 'sys': ['RST-', 'PLLCLK-', 'PLLSELA0-', 'PLLSELA1-', 'PLLTESTOUT+', 'PLLVCOUT+'],
- 'mspi0': ['CK+', 'NSS+', 'MOSI+', 'MISO-'],
- 'eint': eint,
- 'qspi': ['CK+', 'NSS+', 'IO0*', 'IO1*', 'IO2*', 'IO3*'],
- 'sd0': ['CMD*', 'CLK+', 'D0*', 'D1*', 'D2*', 'D3*'],
- }
-
-# testing .....
-p=Platform()
-p.resources=dummy_pinset()
-print(p.resources)
-p.build(Blinker())
\ No newline at end of file
+ 'i2c': ['sda*', 'scl+']}
+
+"""
+a function is needed which turns the results of dummy_pinset()
+into:
+
+[UARTResource("uart", 0, tx=..., rx=..),
+ I2CResource("i2c", 0, scl=..., sda=...),
+ Resource("gpio", 0, Subsignal("i"...), Subsignal("o"...)
+ Resource("gpio", 1, Subsignal("i"...), Subsignal("o"...)
+ ...
+]
+"""
+
+
+def create_resources(pinset):
+ resources = []
+ for periph, pins in pinset.items():
+ print(periph, pins)
+ if periph == 'i2c':
+ #print("I2C required!")
+ resources.append(I2CResource('i2c', 0, sda='sda', scl='scl'))
+ elif periph == 'uart':
+ #print("UART required!")
+ resources.append(UARTResource('uart', 0, tx='tx', rx='rx'))
+ elif periph == 'gpio':
+ #print("GPIO required!")
+ print ("GPIO is defined as '*' type, meaning i, o and oe needed")
+ resources.append(Resource('gpio', 0,
+ Subsignal("i", Pins('i0', dir="i", conn=None, assert_width=1)),
+ Subsignal("oe", Pins('oe0', dir="o", conn=None, assert_width=1)),
+ Subsignal("o", Pins('o0', dir="o", conn=None, assert_width=1))))
+ return resources
+
+
+def UARTResource(*args, rx, tx):
+ io = []
+ io.append(Subsignal("rx", Pins(rx, dir="i", assert_width=1)))
+ io.append(Subsignal("tx", Pins(tx, dir="o", assert_width=1)))
+ return Resource.family(*args, default_name="uart", ios=io)
+
+
+def I2CResource(*args, scl, sda):
+ io = []
+ io.append(Subsignal("scl", Pins(scl, dir="io", assert_width=1)))
+ io.append(Subsignal("sda", Pins(sda, dir="io", assert_width=1)))
+ return Resource.family(*args, default_name="i2c", ios=io)
+
+
+# ridiculously-simple top-level module. doesn't even have a sync domain
+# and can't have one until a clock has been established by DummyPlatform.
+class Blinker(Elaboratable):
+ def __init__(self):
+ pass
+ def elaborate(self, platform):
+ m = Module()
+ count = Signal(5)
+ m.d.comb += count.eq(5)
+ return m
+
+
+# sigh, have to create a dummy platform for now.
+# TODO: investigate how the heck to get it to output ilang. or verilog.
+# or, anything, really. but at least it doesn't barf
+class DummyPlatform(TemplatedPlatform):
+ resources = []
+ connectors = []
+ required_tools = []
+ command_templates = ['/bin/true']
+ file_templates = TemplatedPlatform.build_script_templates
+ toolchain = None
+ def __init__(self, resources):
+ self.resources = resources
+ super().__init__()
+
+"""
+and to create a Platform instance with that list, and build
+something random
+
+ p=Platform()
+ p.resources=listofstuff
+ p.build(Blinker())
+"""
+pinset = dummy_pinset()
+resources = create_resources(pinset)
+print(pinset)
+print(resources)
+p = DummyPlatform (resources)
+p.resources = create_resources(pinset)
+p.build(Blinker())
+
projects / pinmux.git / blobdiff