more messing about

[pinmux.git] / src / spec / testing_stage1.py

diff --git a/src/spec/testing_stage1.py b/src/spec/testing_stage1.py
index fc990e5514fd025a0036896688d3b6c37eb9918b..d543fd0a8283d03c9dfec3fc738b3f33a3857308 100644 (file)
--- a/src/spec/testing_stage1.py
+++ b/src/spec/testing_stage1.py
@@ -144,7 +144,8 @@ def I2CResource(*args, scl, sda):
 
 # top-level demo module.
 class Blinker(Elaboratable):
-    def __init__(self, pinset, resources):
+    def __init__(self, pinset, resources, no_jtag_connect=False):
+        self.no_jtag_connect = no_jtag_connect
         self.jtag = JTAG({}, "sync", resources=resources)
         #memory = Memory(width=32, depth=16)
         #self.sram = SRAM(memory=memory, bus=self.jtag.wb)
@@ -167,7 +168,7 @@ class Blinker(Elaboratable):
         m.d.sync += count[0].eq(gpio.gpio1.i)
         # get the UART resource, mess with the output tx
         uart = self.jtag.request('uart')
-        print (uart, uart.fields)
+        print ("uart fields", uart, uart.fields)
         self.intermediary = Signal()
         m.d.comb += uart.tx.eq(self.intermediary)
         m.d.comb += self.intermediary.eq(uart.rx)
@@ -177,6 +178,10 @@ class Blinker(Elaboratable):
         self.gpio = gpio
         self.uart = uart
 
+        # sigh these wire up to the pads so you cannot set Signals
+        # that are already wired
+        if self.no_jtag_connect: # bypass jtag pad connect for testing purposes
+            return m
         return self.jtag.boundary_elaborate(m, platform)
 
     def ports(self):
@@ -379,7 +384,7 @@ if False:
 def test_case0():
     print("Starting sanity test case!")
     print("printing out list of stuff in top")
-    print(dir(top))
+    print ("JTAG IOs", top.jtag.ios)
     # ok top now has a variable named "gpio", let's enumerate that too
     print("printing out list of stuff in top.gpio and its type")
     print(top.gpio.__class__.__name__, dir(top.gpio))
@@ -391,24 +396,55 @@ def test_case0():
     print("Fun never ends...")
     print("    layout, gpio2:", top.gpio.layout['gpio2'])
     print("    fields, gpio2:", top.gpio.fields['gpio2'])
+    print(top.jtag.__class__.__name__, dir(top.jtag))
+
     # etc etc. you get the general idea
     delayVal = 0.2e-6
     yield top.uart.rx.eq(0)
     yield Delay(delayVal)
     yield Settle()
     yield top.gpio.gpio2.o.eq(0)
+    yield top.gpio.gpio3.o.eq(1)
     yield Delay(delayVal)
     yield Settle()
     yield top.gpio.gpio2.oe.eq(1)
+    yield top.gpio.gpio3.oe.eq(1)
+    #yield top.jtag.gpio.gpio2.i.eq(1)
     yield Delay(delayVal)
     yield Settle()
-    for _ in range(21):
-        yield top.gpio.gpio2.o.eq(~top.gpio.gpio0.o)
+    gpio_o2 = 0
+    for _ in range(20):
+        # get a value first (as an integer).  you were trying to set
+        # it to the actual Signal.  this is not going to work.  or if
+        # it does, it's very scary.
+        gpio_o2 = not gpio_o2
+        yield top.gpio.gpio2.o.eq(gpio_o2)
+
+        # ditto: here you are trying to set to an AST expression
+        # which is inadviseable (likely to fail)
+        yield top.gpio.gpio3.o.eq(~top.gpio.gpio3.o)
         yield Delay(delayVal)
         yield Settle()
-        yield top.uart.rx.eq(~top.intermediary)
+        # grab the JTAG resource pad
+        uart_pad = top.jtag.resource_table_pads[('uart', 0)]
+        yield uart_pad.rx.i.eq(gpio_o2)
         yield Delay(delayVal)
         yield Settle()
+        yield # one clock cycle
+        tx_val = yield uart_pad.tx.o
+        print ("xmit uart", tx_val, gpio_o2)
+    
+    print ("jtag pad table keys")
+    print (top.jtag.resource_table_pads.keys())
+    uart_pad = top.jtag.resource_table_pads[('uart', 0)]
+    print ("uart pad", uart_pad)
+    print ("uart pad", uart_pad.layout)
+
+    yield top.gpio.gpio2.oe.eq(0)
+    yield top.gpio.gpio3.oe.eq(0)
+    #yield top.jtag.gpio.gpio2.i.eq(0)
+    yield Delay(delayVal)
+    yield Settle()
 
 # Code borrowed from cesar, runs, but shouldn't actually work because of
 # self. statements and non-existent signal names.