get access to jtag boundary scan pads for uart_0_tx/rx

[pinmux.git] / src / spec / testing_stage1.py

diff --git a/src/spec/testing_stage1.py b/src/spec/testing_stage1.py
index f57ca239022a637d1189a9bde407d1d8e6d0850c..fe5143179b3139b50e199b76b980116486ca3408 100644 (file)
--- a/src/spec/testing_stage1.py
+++ b/src/spec/testing_stage1.py
@@ -201,10 +201,27 @@ class Blinker(Elaboratable):
         m.d.comb += uart.tx.eq(self.intermediary)
         m.d.comb += self.intermediary.eq(uart.rx)
 
+        # I2C
+        num_i2c = 1
+        i2c_sda_oe_test = Signal(num_i2c)
+        i2c_scl_oe_test = Signal(num_i2c)
+        i2c = self.jtag.request('i2c')
+        print ("i2c fields", i2c, i2c.fields)
+        # Connect in loopback
+        m.d.comb += i2c.scl.o.eq(i2c.scl.i)
+        m.d.comb += i2c.sda.o.eq(i2c.sda.i)
+        # Connect output enable to test port for sim
+        m.d.comb += i2c.sda.oe.eq(i2c_sda_oe_test)
+        m.d.comb += i2c.scl.oe.eq(i2c_scl_oe_test)
+
         # to even be able to get at objects, you first have to make them
         # available - i.e. not as local variables
+        # Public attributes are equivalent to input/output ports in hdl's
         self.gpio = gpio
         self.uart = uart
+        self.i2c = i2c
+        self.i2c_sda_oe_test = i2c_sda_oe_test
+        self.i2c_scl_oe_test = i2c_scl_oe_test
         self.gpio_i_ro = gpio_i_ro
         self.gpio_o_test = gpio_o_test
         self.gpio_oe_test = gpio_oe_test
@@ -560,7 +577,66 @@ def test_gpios():
         #print("---------------------") 
     print("GPIO Test PASSED!")
 
-     
+def test_uart():
+    # grab the JTAG resource pad
+    print ()
+    print ("bs pad keys", top.jtag.boundary_scan_pads.keys())
+    print ()
+    uart_rx_pad = top.jtag.boundary_scan_pads['uart_0__rx']['i']
+    uart_tx_pad = top.jtag.boundary_scan_pads['uart_0__tx']['o']
+
+    print ("uart rx pad", uart_rx_pad)
+    print ("uart tx pad", uart_tx_pad)
+
+    # Test UART by writing 0 and 1 to RX
+    # Internally TX connected to RX,
+    # so match pad TX with RX
+    for i in range(0, 2):
+        yield uart_rx_pad.eq(i)
+        #yield uart_rx_pad.eq(i)
+        yield Settle()
+        yield # one clock cycle
+        tx_val = yield uart_tx_pad
+        print ("xmit uart", tx_val, 1)
+        assert tx_val == i
+
+    print("UART Test PASSED!")
+
+def test_i2c():
+    i2c_sda_i_pad = top.jtag.boundary_scan_pads['i2c_0__sda__i']['i']
+    i2c_sda_o_pad = top.jtag.boundary_scan_pads['i2c_0__sda__o']['o']
+    i2c_sda_oe_pad = top.jtag.boundary_scan_pads['i2c_0__sda__oe']['o']
+
+    i2c_scl_i_pad = top.jtag.boundary_scan_pads['i2c_0__scl__i']['i']
+    i2c_scl_o_pad = top.jtag.boundary_scan_pads['i2c_0__scl__o']['o']
+    i2c_scl_oe_pad = top.jtag.boundary_scan_pads['i2c_0__scl__oe']['o']
+
+    #i2c_pad = top.jtag.resource_table_pads[('i2c', 0)]
+    #print ("i2c pad", i2c_pad)
+    #print ("i2c pad", i2c_pad.layout)
+
+    for i in range(0, 2):
+        yield i2c_sda_i_pad.eq(i) #i2c_pad.sda.i.eq(i)
+        yield i2c_scl_i_pad.eq(i) #i2c_pad.scl.i.eq(i)
+        yield top.i2c_sda_oe_test.eq(i)
+        yield top.i2c_scl_oe_test.eq(i)
+        yield Settle()
+        yield # one clock cycle
+        sda_o_val = yield i2c_sda_o_pad
+        scl_o_val = yield i2c_scl_o_pad
+        sda_oe_val = yield i2c_sda_oe_pad
+        scl_oe_val = yield i2c_scl_oe_pad
+        print ("Test input: ", i, " SDA/SCL out: ", sda_o_val, scl_o_val,
+               " SDA/SCL oe: ", sda_oe_val, scl_oe_val)
+        assert sda_o_val == i
+        assert scl_o_val == i
+        assert sda_oe_val == i
+        assert scl_oe_val == i
+
+    print("I2C Test PASSED!")
+
+
+
 def test_debug_print():
     print("Test used for getting object methods/information")
     print("Moved here to clear clutter of gpio test")
@@ -570,7 +646,7 @@ def test_debug_print():
     print ("this is a PIN resource", type(top.gpio['gpio0']['i']))
     # yield can only be done on SIGNALS or RECORDS,
     # NOT Pins/Resources gpio0_core_in = yield top.gpio['gpio0']['i']
-    print("Test gpio0 core in: ", gpio0_core_in)
+    #print("Test gpio0 core in: ", gpio0_core_in)
     
     print("JTAG")
     print(top.jtag.__class__.__name__, dir(top.jtag))
@@ -580,12 +656,31 @@ def test_debug_print():
     print(top.ports.__class__.__name__, dir(top.ports))
     print("GPIO")
     print(top.gpio.__class__.__name__, dir(top.gpio))
-    
+   
+    print("UART")
+    print(dir(top.jtag.boundary_scan_pads['uart_0__rx__pad__i']))
+    print(top.jtag.boundary_scan_pads['uart_0__rx__pad__i'].keys())
+    print(top.jtag.boundary_scan_pads['uart_0__tx__pad__o'])
+    #print(type(top.jtag.boundary_scan_pads['uart_0__rx__pad__i']['rx']))
+    print ("jtag pad table keys")
+    print (top.jtag.resource_table_pads.keys())
+    print(type(top.jtag.resource_table_pads[('uart', 0)].rx.i))
+    print(top.jtag.boundary_scan_pads['uart_0__rx__i'])
+
+    print("I2C")
+    print(top.jtag.boundary_scan_pads['i2c_0__sda__i'])
+    print(type(top.jtag.boundary_scan_pads['i2c_0__sda__i']['i']))
+
+    print(top.jtag.resource_table_pads)
+    print(top.jtag.boundary_scan_pads)
+
+
     # Trying to read input from core side, looks like might be a pin...
     # XXX don't "look like" - don't guess - *print it out*
     #print ("don't guess, CHECK", type(top.gpio.gpio0.i))
     
     print () # extra print to divide the output
+    yield
 
 if __name__ == '__main__':
     """
@@ -657,7 +752,11 @@ if __name__ == '__main__':
     
     #sim.add_sync_process(wrap(test_case1()))
     #sim.add_sync_process(wrap(test_case0()))
-    sim.add_sync_process(wrap(test_gpios()))
+    
+    #sim.add_sync_process(wrap(test_gpios()))
+    sim.add_sync_process(wrap(test_uart()))
+    sim.add_sync_process(wrap(test_i2c()))
+    #sim.add_sync_process(wrap(test_debug_print()))
 
     with sim.write_vcd("blinker_test.vcd"):
         sim.run()