Add Tercel PHY reset synchronization

[microwatt.git] / tercel / phy.v

diff --git a/tercel/phy.v b/tercel/phy.v
index 57cbe2c07c4122d19872bba60dddc4a2f4d12a7d..b3600a279a58dbc75102ed14c384aa90d090f6e2 100644 (file)
--- a/tercel/phy.v
+++ b/tercel/phy.v
@@ -1,4 +1,4 @@
-// © 2017 - 2021 Raptor Engineering, LLC
+// © 2017 - 2022 Raptor Engineering, LLC
 //
 // Released under the terms of the GPL v3
 // See the LICENSE file for full details
@@ -9,6 +9,7 @@
 module spi_master_phy_quad(
                input wire platform_clock,
                input wire reset,
+               output wire ready,
                input wire [31:0] tx_data,
                output reg [31:0] rx_data,
                input wire [7:0] dummy_cycle_count,
@@ -33,6 +34,8 @@ module spi_master_phy_quad(
                output reg spi_quad_mode_pin_enable
        );
 
+       reg phy_ready = 0;
+
        reg [3:0] transfer_state = 0;
        reg [31:0] data_shift_out = 0;
 
@@ -46,8 +49,11 @@ module spi_master_phy_quad(
        reg [7:0] sspi_transfer_cycle_stop_value = 0;
        reg [3:0] qspi_transfer_cycle_stop_value = 0;
 
+       assign ready = phy_ready;
+
        always @(posedge platform_clock) begin
                if (reset) begin
+                       phy_ready <= 0;
                        transfer_state <= 0;
                        state_iteration <= 0;
                        transaction_complete <= 1;
@@ -93,12 +99,14 @@ module spi_master_phy_quad(
                                                spi_ss_n <= 1'b0;
 
                                                transfer_state <= 1;
+                                               phy_ready <= 0;
                                        end else begin
                                                if (!hold_ss_active) begin
                                                        ss_state_at_idle <= 1'b1;
                                                end
                                                spi_quad_mode_pin_enable <= 0;
                                                transfer_state <= 0;
+                                               phy_ready <= 1;
                                        end
                                end
                                1: begin