Add Tercel PHY reset synchronization

[microwatt.git] / wishbone_types.vhdl

diff --git a/wishbone_types.vhdl b/wishbone_types.vhdl
index 693deacf5859f1f708c6954b1cc026db5b9c1002..210ac43ba247a21eb628087bf4fd4b9fd2fedc11 100644 (file)
--- a/wishbone_types.vhdl
+++ b/wishbone_types.vhdl
@@ -16,9 +16,9 @@ package wishbone_types is
     type wishbone_master_out is record
         adr : wishbone_addr_type;
         dat : wishbone_data_type;
+        sel : wishbone_sel_type;
         cyc : std_ulogic;
         stb : std_ulogic;
-        sel : wishbone_sel_type;
         we  : std_ulogic;
     end record;
     constant wishbone_master_out_init : wishbone_master_out := (adr => (others => '0'), dat => (others => '0'), cyc => '0', stb => '0', sel => (others => '0'), we => '0');
@@ -50,5 +50,5 @@ package wishbone_types is
         ack   : std_ulogic;
         stall : std_ulogic;
     end record;
-    
+    constant wb_io_slave_out_init : wb_io_slave_out := (ack => '0', stall => '0', others => (others => '0'));
 end package wishbone_types;