port (
clk : in std_logic;
- m_in : in Execute1ToMultiplyType;
- m_out : out MultiplyToExecute1Type
+ m_in : in MultiplyInputType;
+ m_out : out MultiplyOutputType
);
end entity multiply;
signal p1_pat, p1_patb : std_ulogic;
signal req_32bit, r32_1 : std_ulogic;
- signal req_neg, rneg_1 : std_ulogic;
+ signal req_not, rnot_1 : std_ulogic;
signal valid_1 : std_ulogic;
+ signal overflow, ovf_in : std_ulogic;
begin
- addend <= (others => m_in.neg_result);
+ addend <= m_in.addend;
m00: DSP48E1
generic map (
CECTRL => '0',
CED => '0',
CEINMODE => '0',
- CEM => '1',
+ CEM => m_in.valid,
CEP => '0',
CLK => clk,
D => (others => '0'),
CECTRL => '0',
CED => '0',
CEINMODE => '0',
- CEM => '1',
+ CEM => m_in.valid,
CEP => '0',
CLK => clk,
D => (others => '0'),
CECTRL => '0',
CED => '0',
CEINMODE => '0',
- CEM => '1',
+ CEM => m_in.valid,
CEP => '0',
CLK => clk,
D => (others => '0'),
CECTRL => '0',
CED => '0',
CEINMODE => '0',
- CEM => '1',
+ CEM => m_in.valid,
CEP => '0',
CLK => clk,
D => (others => '0'),
CECTRL => '0',
CED => '0',
CEINMODE => '0',
- CEM => '1',
+ CEM => m_in.valid,
CEP => '0',
CLK => clk,
D => (others => '0'),
CECTRL => '0',
CED => '0',
CEINMODE => '0',
- CEM => '1',
+ CEM => m_in.valid,
CEP => '0',
CLK => clk,
D => (others => '0'),
CECTRL => '0',
CED => '0',
CEINMODE => '0',
- CEM => '1',
+ CEM => m_in.valid,
CEP => '0',
CLK => clk,
D => (others => '0'),
CECTRL => '0',
CED => '0',
CEINMODE => '0',
- CEM => '1',
+ CEM => m_in.valid,
CEP => '0',
CLK => clk,
D => (others => '0'),
CECTRL => '0',
CED => '0',
CEINMODE => '0',
- CEM => '1',
+ CEM => m_in.valid,
CEP => '0',
CLK => clk,
D => (others => '0'),
CECTRL => '0',
CED => '0',
CEINMODE => '0',
- CEM => '1',
+ CEM => m_in.valid,
CEP => '0',
CLK => clk,
D => (others => '0'),
CECTRL => '0',
CED => '0',
CEINMODE => '0',
- CEM => '1',
+ CEM => m_in.valid,
CEP => '0',
CLK => clk,
D => (others => '0'),
CECTRL => '0',
CED => '0',
CEINMODE => '0',
- CEM => '1',
+ CEM => m_in.valid,
CEP => '0',
CLK => clk,
D => (others => '0'),
CARRYINSEL => "000",
CARRYOUT => s0_carry,
CEA1 => '0',
- CEA2 => '1',
+ CEA2 => valid_1,
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
- CEB2 => '1',
- CEC => '1',
+ CEB2 => valid_1,
+ CEC => valid_1,
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CARRYIN => s0_carry(3),
CARRYINSEL => "000",
CEA1 => '0',
- CEA2 => '1',
+ CEA2 => valid_1,
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
- CEB2 => '1',
- CEC => '1',
+ CEB2 => valid_1,
+ CEC => valid_1,
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
port map (
A => m21_p(22 downto 0) & m03_p(5 downto 0) & '0',
ACIN => (others => '0'),
- ALUMODE => "00" & rneg_1 & '0',
+ ALUMODE => "00" & rnot_1 & '0',
B => (others => '0'),
BCIN => (others => '0'),
C => p0_mask,
CARRYINSEL => "000",
CARRYOUT => p0_carry,
CEA1 => '0',
- CEA2 => '1',
+ CEA2 => valid_1,
CEAD => '0',
- CEALUMODE => '1',
+ CEALUMODE => valid_1,
CEB1 => '0',
- CEB2 => '1',
- CEC => '1',
+ CEB2 => valid_1,
+ CEC => valid_1,
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
port map (
A => x"0000000" & '0' & m21_p(41),
ACIN => (others => '0'),
- ALUMODE => "00" & rneg_1 & '0',
+ ALUMODE => "00" & rnot_1 & '0',
B => m21_p(40 downto 23),
BCIN => (others => '0'),
C => (others => '0'),
CARRYIN => p0_carry(3),
CARRYINSEL => "000",
CEA1 => '0',
- CEA2 => '1',
+ CEA2 => valid_1,
CEAD => '0',
- CEALUMODE => '1',
+ CEALUMODE => valid_1,
CEB1 => '0',
- CEB2 => '1',
+ CEB2 => valid_1,
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
RSTP => '0'
);
- product(31 downto 0) <= product_lo xor (31 downto 0 => req_neg);
+ product(31 downto 0) <= product_lo xor (31 downto 0 => req_not);
mult_out: process(all)
variable ov : std_ulogic;
ov := not ((p1_pat and p0_pat and not product(31)) or
(p1_patb and p0_patb and product(31)));
end if;
+ ovf_in <= ov;
m_out.result <= product;
- m_out.overflow <= ov;
+ m_out.overflow <= overflow;
end process;
process(clk)
valid_1 <= m_in.valid;
req_32bit <= r32_1;
r32_1 <= m_in.is_32bit;
- req_neg <= rneg_1;
- rneg_1 <= m_in.neg_result;
+ req_not <= rnot_1;
+ rnot_1 <= m_in.not_result;
+ overflow <= ovf_in;
end if;
end process;