X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;ds=sidebyside;f=src%2Fmain%2Fscala%2Fdevices%2Fi2c%2FI2CPins.scala;h=6ad1783d4da5379453830b4481d676e0e65f1063;hb=38f537c438224418356c1ef6979c482841a0da4c;hp=73f4cfb8ad12d4c4b459650100dc41459ee147cd;hpb=4d74e8f67f871df93f7bb2dfb2fa8bffb641fc4a;p=sifive-blocks.git

diff --git a/src/main/scala/devices/i2c/I2CPins.scala b/src/main/scala/devices/i2c/I2CPins.scala
index 73f4cfb..6ad1783 100644
--- a/src/main/scala/devices/i2c/I2CPins.scala
+++ b/src/main/scala/devices/i2c/I2CPins.scala
@@ -2,22 +2,34 @@
 package sifive.blocks.devices.i2c
 
 import Chisel._
+import chisel3.experimental.{withClockAndReset}
+import freechips.rocketchip.util.SyncResetSynchronizerShiftReg
 import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
-import sifive.blocks.util.ShiftRegisterInit
 
-
-class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
+class I2CSignals[T <: Data](pingen: () => T) extends Bundle {
 
   val scl: T = pingen()
   val sda: T = pingen()
 
-  def fromI2CPort(i2c: I2CPort, syncStages: Int = 0) = {
-    scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
-    scl.o.oe := i2c.scl.oe
-    i2c.scl.in := ShiftRegisterInit(scl.i.ival, syncStages, Bool(true))
+  override def cloneType: this.type =
+    this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
+}
+
+class I2CPins[T <: Pin](pingen: () => T) extends I2CSignals[T](pingen) {
+  override def cloneType: this.type =
+    this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
+
+  def fromPort(i2c: I2CPort, clock: Clock, reset: Bool, syncStages: Int = 0) = {
+    withClockAndReset(clock, reset) {
+      scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
+      scl.o.oe := i2c.scl.oe
+      i2c.scl.in := SyncResetSynchronizerShiftReg(scl.i.ival, syncStages, init = Bool(true),
+        name = Some("i2c_scl_sync"))
 
-    sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
-    sda.o.oe := i2c.sda.oe
-    i2c.sda.in := ShiftRegisterInit(sda.i.ival, syncStages, Bool(true))
+      sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
+      sda.o.oe := i2c.sda.oe
+      i2c.sda.in := SyncResetSynchronizerShiftReg(sda.i.ival, syncStages, init = Bool(true),
+        name = Some("i2c_sda_sync"))
+    }
   }
 }