X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=Makefile;h=15670cf8b3babf7f8e0991cd3e5100fecb68d273;hb=7c41d80d9a1af94f8dacd808b822bee62a620811;hp=2a6409b663126891d5d8b3687aca4598551fbdd4;hpb=8e00e09b914b9fa3af430c2f913a9921207063cd;p=soc.git

diff --git a/Makefile b/Makefile
index 2a6409b6..15670cf8 100644
--- a/Makefile
+++ b/Makefile
@@ -63,6 +63,14 @@ microwatt_external_core:
 	python3 src/soc/simple/issuer_verilog.py --microwatt-compat --enable-mmu \
             external_core_top.v
 
+# build microwatt "external core" with fixed 64-bit width SVP64
+# note that the TLB set size is set to 16
+# for I/D-Cache which needs a corresponding alteration of the device-tree
+# entries for linux
+microwatt_external_core_svp64:
+	python3 src/soc/simple/issuer_verilog.py --microwatt-compat-svp64 --enable-mmu \
+            external_core_top.v
+
 microwatt_external_core_spi:
 	python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
             --small-cache \