X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=Makefile;h=20bce282fdd9dc00c6ecea00bb78c6061dcb72f8;hb=2bdaa48f551195d619a096cb14cf7e3683f4dd48;hp=3d4ea62db5a779f896d1f59665014783681f0523;hpb=205af15112e2dcd44b6f1d29ef032b528666a18d;p=soc.git

diff --git a/Makefile b/Makefile
index 3d4ea62d..20bce282 100644
--- a/Makefile
+++ b/Makefile
@@ -56,6 +56,11 @@ ls180_4k_verilog:
 	        --enable-xics --enable-sram4x4kblock --disable-svp64 \
 			src/soc/litex/florent/libresoc/libresoc.v
 
+# build microwatt "external core"
+microwatt_external_core:
+	python3 simple/issuer_verilog.py --microwatt-compat --enable-mmu \
+            external_core_top.v
+
 # build the litex libresoc SoC without 4k SRAMs
 ls180_verilog_build: ls180_verilog
 	make -C soc/soc/litex/florent ls180