X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=Makefile;h=736cd7b1ac2ace8e379e6a941d3e1f0adaf4c0de;hb=b263f3f6f134c2f1d9be78d69b1799b3fbd90b4d;hp=f318ae315da4e8b0b21fe6d2ab1f44fdb9817c1a;hpb=8c449e2782facaa874b7820627565a1edb4111da;p=soc.git

diff --git a/Makefile b/Makefile
index f318ae31..736cd7b1 100644
--- a/Makefile
+++ b/Makefile
@@ -69,6 +69,12 @@ microwatt_external_core_spi:
             --pc-reset 0x10000000 \
             external_core_top.v
 
+microwatt_external_core_bram:
+	python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
+            --enable-mmu \
+            --pc-reset 0xFFF00000 \
+            external_core_top.v
+
 # build the litex libresoc SoC without 4k SRAMs
 ls180_verilog_build: ls180_verilog
 	make -C soc/soc/litex/florent ls180