X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=Makefile;h=8d379590387090fa04a28b2b64ebac56c26231ec;hb=c18d53f534d25eb9728480b62e3fa0f0be13f96f;hp=736cd7b1ac2ace8e379e6a941d3e1f0adaf4c0de;hpb=3d1fbb5790eaf4b74a96f16dc53369b458b2a727;p=soc.git

diff --git a/Makefile b/Makefile
index 736cd7b1..8d379590 100644
--- a/Makefile
+++ b/Makefile
@@ -72,7 +72,7 @@ microwatt_external_core_spi:
 microwatt_external_core_bram:
 	python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
             --enable-mmu \
-            --pc-reset 0xFFF00000 \
+            --pc-reset 0xFF000000 \
             external_core_top.v
 
 # build the litex libresoc SoC without 4k SRAMs