X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=benchmarks%2Fvec-cmplxmult%2Fvec_cmplxmult_asm.S;h=9ccd6c2d103ca1e16e5c6511ca356ab81dc58dda;hb=5fe2ce69dcd1d0ddb42c4edffac7ab11d939ca45;hp=07719656432721ed1ee186cf8ae71e3bbe9cd159;hpb=5b13eb6cd5aa3e73fb477414f1866e7b9cbeaf3f;p=riscv-tests.git

diff --git a/benchmarks/vec-cmplxmult/vec_cmplxmult_asm.S b/benchmarks/vec-cmplxmult/vec_cmplxmult_asm.S
index 0771965..9ccd6c2 100644
--- a/benchmarks/vec-cmplxmult/vec_cmplxmult_asm.S
+++ b/benchmarks/vec-cmplxmult/vec_cmplxmult_asm.S
@@ -21,9 +21,9 @@
 #define rVlen   a6
 #define rStride a7
 
-#define rAI a8
-#define rBI a9
-#define rCI a10
+#define rAI t0
+#define rBI t1
+#define rCI t2
 
 # WARNING: do not write to the s0,...,s9 registers without first saving them to
 # the stack.