X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=common.mk;h=e23cbb7eaed1a1d9815b6db3eda48f4025452dfa;hb=e1673b86705f0fc3f812a46bd08c4ae7ff054fa3;hp=74f74de59c40891b8f4ea9af77366e8cfc772363;hpb=c14985f3a78aa0f19f4e4c3eae42a3e8e512910c;p=freedom-sifive.git

diff --git a/common.mk b/common.mk
index 74f74de..e23cbb7 100644
--- a/common.mk
+++ b/common.mk
@@ -11,11 +11,23 @@
 # Optional variables:
 # - EXTRA_FPGA_VSRCS
 
+# export to bootloader
+export ROMCONF=$(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.conf
+
+# export to fpga-shells
+export FPGA_TOP_SYSTEM=$(MODEL)
+export FPGA_BUILD_DIR=$(BUILD_DIR)/$(FPGA_TOP_SYSTEM)
+export fpga_common_script_dir=$(FPGA_DIR)/common/tcl
+export fpga_board_script_dir=$(FPGA_DIR)/$(BOARD)/tcl
+
+export BUILD_DIR
+
 EXTRA_FPGA_VSRCS ?=
 PATCHVERILOG ?= ""
+BOOTROM_DIR ?= ""
 
 base_dir := $(patsubst %/,%,$(dir $(abspath $(lastword $(MAKEFILE_LIST)))))
-rocketchip_dir := $(base_dir)/rocket-chip
+export rocketchip_dir := $(base_dir)/rocket-chip
 SBT ?= java -jar $(rocketchip_dir)/sbt-launch.jar
 
 # Build firrtl.jar and put it where chisel3 can find it.
@@ -25,15 +37,16 @@ FIRRTL ?= java -Xmx2G -Xss8M -XX:MaxPermSize=256M -cp $(FIRRTL_JAR) firrtl.Drive
 $(FIRRTL_JAR): $(shell find $(rocketchip_dir)/firrtl/src/main/scala -iname "*.scala")
 	$(MAKE) -C $(rocketchip_dir)/firrtl SBT="$(SBT)" root_dir=$(rocketchip_dir)/firrtl build-scala
 	touch $(FIRRTL_JAR)
+	mkdir -p $(rocketchip_dir)/lib
+	cp -p $(FIRRTL_JAR) rocket-chip/lib
 	mkdir -p $(rocketchip_dir)/chisel3/lib
 	cp -p $(FIRRTL_JAR) $(rocketchip_dir)/chisel3/lib
 
 # Build .fir
 firrtl := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).fir
-firrtl_prm := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).prm
-$(firrtl) $(firrtl_prm): $(shell find $(base_dir)/src/main/scala -name '*.scala') $(FIRRTL_JAR)
+$(firrtl): $(shell find $(base_dir)/src/main/scala -name '*.scala') $(FIRRTL_JAR)
 	mkdir -p $(dir $@)
-	$(SBT) "run-main rocketchip.Generator $(BUILD_DIR) $(PROJECT) $(MODEL) $(CONFIG_PROJECT) $(CONFIG)"
+	$(SBT) "run-main freechips.rocketchip.system.Generator $(BUILD_DIR) $(PROJECT) $(MODEL) $(CONFIG_PROJECT) $(CONFIG)"
 
 .PHONY: firrtl
 firrtl: $(firrtl)
@@ -46,15 +59,39 @@ ifneq ($(PATCHVERILOG),"")
 	$(PATCHVERILOG)
 endif
 
-
 .PHONY: verilog
 verilog: $(verilog)
 
+romgen := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).rom.v
+$(romgen): $(verilog)
+ifneq ($(BOOTROM_DIR),"")
+	$(MAKE) -C $(BOOTROM_DIR) romgen
+	mv $(BUILD_DIR)/rom.v $@
+endif
+
+.PHONY: romgen
+romgen: $(romgen)
+
+f := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).vsrcs.F
+$(f):
+	echo $(VSRCS) > $@
+
+bit := $(BUILD_DIR)/obj/$(MODEL).bit
+$(bit): $(romgen) $(f)
+	cd $(BUILD_DIR); vivado \
+		-nojournal -mode batch \
+		-source $(fpga_common_script_dir)/vivado.tcl \
+		-tclargs \
+		-top-module "$(MODEL)" \
+		-F "$(f)" \
+		-ip-vivado-tcls "$(shell find '$(BUILD_DIR)' -name '*.vivado.tcl')" \
+		-board "$(BOARD)"
+
+
 # Build .mcs
-mcs := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).mcs
-$(mcs): $(verilog)
-	VSRC_TOP=$(verilog) EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) mcs
-	cp $(FPGA_DIR)/obj/system.mcs $@
+mcs := $(BUILD_DIR)/obj/$(MODEL).mcs
+$(mcs): $(bit)
+	cd $(BUILD_DIR); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $<
 
 .PHONY: mcs
 mcs: $(mcs)
@@ -62,5 +99,8 @@ mcs: $(mcs)
 # Clean
 .PHONY: clean
 clean:
+ifneq ($(BOOTROM_DIR),"")
+	$(MAKE) -C $(BOOTROM_DIR) clean
+endif
 	$(MAKE) -C $(FPGA_DIR) clean
 	rm -rf $(BUILD_DIR)