X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=config.h.in;h=137f1950054e3e4b709a76233c2aadcee778c7cf;hb=3582bab41908a649c975ae98ad97a0d84b48dcde;hp=15b5850defa329b48c47ef2f55c6f8f0c2bd7b71;hpb=c71db7787b63fc1ab0c57672c9e469711748bda9;p=riscv-isa-sim.git

diff --git a/config.h.in b/config.h.in
index 15b5850..137f195 100644
--- a/config.h.in
+++ b/config.h.in
@@ -75,6 +75,9 @@
 /* Enable PC histogram generation */
 #undef RISCV_ENABLE_HISTOGRAM
 
+/* Enable hardware support for misaligned loads and stores */
+#undef RISCV_ENABLE_MISALIGNED
+
 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
 #undef SOFTFLOAT_ENABLED