X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=config.h.in;h=137f1950054e3e4b709a76233c2aadcee778c7cf;hb=3582bab41908a649c975ae98ad97a0d84b48dcde;hp=a4070ff0adba26218f0e45ad320ca023917c53a8;hpb=10ae74e48aee7403bc3cb2540d1a7ccb7c69a211;p=riscv-isa-sim.git

diff --git a/config.h.in b/config.h.in
index a4070ff..137f195 100644
--- a/config.h.in
+++ b/config.h.in
@@ -6,6 +6,9 @@
 /* Default value for --isa switch */
 #undef DEFAULT_ISA
 
+/* Path to the device-tree-compiler */
+#undef DTC
+
 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
 #undef DUMMY_ROCC_ENABLED
 
@@ -66,9 +69,15 @@
 /* Enable commit log generation */
 #undef RISCV_ENABLE_COMMITLOG
 
+/* Enable hardware management of PTE accessed and dirty bits */
+#undef RISCV_ENABLE_DIRTY
+
 /* Enable PC histogram generation */
 #undef RISCV_ENABLE_HISTOGRAM
 
+/* Enable hardware support for misaligned loads and stores */
+#undef RISCV_ENABLE_MISALIGNED
+
 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
 #undef SOFTFLOAT_ENABLED