X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=config.h.in;h=137f1950054e3e4b709a76233c2aadcee778c7cf;hb=526d3997e68200ef3f372384acdc13e8e8b92e31;hp=52c725334ffdea85adc4ba99a916becf33cd8e7c;hpb=e104cd11f504c2de3d1fdfa2ce9193f8f878d15c;p=riscv-isa-sim.git diff --git a/config.h.in b/config.h.in index 52c7253..137f195 100644 --- a/config.h.in +++ b/config.h.in @@ -1,16 +1,49 @@ /* config.h.in. Generated from configure.ac by autoheader. */ +/* Define if building universal (internal helper macro) */ +#undef AC_APPLE_UNIVERSAL_BUILD + +/* Default value for --isa switch */ +#undef DEFAULT_ISA + +/* Path to the device-tree-compiler */ +#undef DTC + /* Define if subproject MCPPBS_SPROJ_NORM is enabled */ #undef DUMMY_ROCC_ENABLED +/* Define to 1 if you have the header file. */ +#undef HAVE_INTTYPES_H + /* Define to 1 if you have the `fesvr' library (-lfesvr). */ #undef HAVE_LIBFESVR /* Define to 1 if you have the `pthread' library (-lpthread). */ #undef HAVE_LIBPTHREAD -/* Define if subproject MCPPBS_SPROJ_NORM is enabled */ -#undef HWACHA_ENABLED +/* Define to 1 if you have the header file. */ +#undef HAVE_MEMORY_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STDINT_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STDLIB_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STRINGS_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_STRING_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_STAT_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_SYS_TYPES_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_UNISTD_H /* Define to the address where bug reports for this package should be sent. */ #undef PACKAGE_BUGREPORT @@ -33,18 +66,18 @@ /* Define if subproject MCPPBS_SPROJ_NORM is enabled */ #undef RISCV_ENABLED -/* Define if 64-bit mode is supported */ -#undef RISCV_ENABLE_64BIT - /* Enable commit log generation */ #undef RISCV_ENABLE_COMMITLOG -/* Define if floating-point instructions are supported */ -#undef RISCV_ENABLE_FPU +/* Enable hardware management of PTE accessed and dirty bits */ +#undef RISCV_ENABLE_DIRTY /* Enable PC histogram generation */ #undef RISCV_ENABLE_HISTOGRAM +/* Enable hardware support for misaligned loads and stores */ +#undef RISCV_ENABLE_MISALIGNED + /* Define if subproject MCPPBS_SPROJ_NORM is enabled */ #undef SOFTFLOAT_ENABLED @@ -53,3 +86,15 @@ /* Define to 1 if you have the ANSI C header files. */ #undef STDC_HEADERS + +/* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most + significant byte first (like Motorola and SPARC, unlike Intel). */ +#if defined AC_APPLE_UNIVERSAL_BUILD +# if defined __BIG_ENDIAN__ +# define WORDS_BIGENDIAN 1 +# endif +#else +# ifndef WORDS_BIGENDIAN +# undef WORDS_BIGENDIAN +# endif +#endif