X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=config.h.in;h=f5608c59388be1b9f9acd47a73b5c07c6a05446b;hb=c4350ef6ef6259e48509e125fd2d051969dc6efa;hp=5293fa8dafc9121be87a0d46ab089f0402964547;hpb=d9d73d80c1b738b3b30eb40d192f61cbdb0e201f;p=riscv-isa-sim.git

diff --git a/config.h.in b/config.h.in
index 5293fa8..f5608c5 100644
--- a/config.h.in
+++ b/config.h.in
@@ -33,21 +33,12 @@
 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
 #undef RISCV_ENABLED
 
-/* Define if 64-bit mode is supported */
-#undef RISCV_ENABLE_64BIT
-
 /* Enable commit log generation */
 #undef RISCV_ENABLE_COMMITLOG
 
-/* Define if floating-point instructions are supported */
-#undef RISCV_ENABLE_FPU
-
 /* Enable PC histogram generation */
 #undef RISCV_ENABLE_HISTOGRAM
 
-/* Define if RISC-V Compressed is supported */
-#undef RISCV_ENABLE_RVC
-
 /* Define if subproject MCPPBS_SPROJ_NORM is enabled */
 #undef SOFTFLOAT_ENABLED