X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=configure;h=015f63e965a04eabe6cecb4d7f984c0e35345476;hb=96218b1cdc0cd395d150e7db08a1b84ea1ae1543;hp=eddc14746644bd2e00a9a248aa95053e4dc54413;hpb=c71db7787b63fc1ab0c57672c9e469711748bda9;p=riscv-isa-sim.git

diff --git a/configure b/configure
index eddc147..015f63e 100755
--- a/configure
+++ b/configure
@@ -706,6 +706,7 @@ with_fesvr
 enable_commitlog
 enable_histogram
 enable_dirty
+enable_misaligned
 '
       ac_precious_vars='build_alias
 host_alias
@@ -1352,6 +1353,8 @@ Optional Features:
   --enable-histogram      Enable PC histogram generation
   --enable-dirty          Enable hardware management of PTE accessed and dirty
                           bits
+  --enable-misaligned     Enable hardware support for misaligned loads and
+                          stores
 
 Optional Packages:
   --with-PACKAGE[=ARG]    use PACKAGE [ARG=yes]
@@ -3406,6 +3409,7 @@ done
   done
 IFS=$as_save_IFS
 
+  test -z "$ac_cv_path_DTC" && ac_cv_path_DTC="no"
   ;;
 esac
 fi
@@ -3419,6 +3423,9 @@ $as_echo "no" >&6; }
 fi
 
 
+if test x"$DTC" == xno; then :
+  as_fn_error $? "device-tree-compiler not found" "$LINENO" 5
+fi
 
 cat >>confdefs.h <<_ACEOF
 #define DTC "$DTC"
@@ -4679,6 +4686,19 @@ if test "x$enable_dirty" = "xyes"; then :
 $as_echo "#define RISCV_ENABLE_DIRTY /**/" >>confdefs.h
 
 
+fi
+
+# Check whether --enable-misaligned was given.
+if test "${enable_misaligned+set}" = set; then :
+  enableval=$enable_misaligned;
+fi
+
+if test "x$enable_misaligned" = "xyes"; then :
+
+
+$as_echo "#define RISCV_ENABLE_MISALIGNED /**/" >>confdefs.h
+
+
 fi