X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=cpu.py;h=01b4e23fa85b84a3a3cfc73d15802ec4f71fddff;hb=56b1de0ace7ac7f5e1e0c5211a025ce15a24a365;hp=7150968bda422e1cac82a9f29341b360e8731ef0;hpb=fdb8299f8fe529c7b4c0a07825f5d8c183a03444;p=rv32.git diff --git a/cpu.py b/cpu.py index 7150968..01b4e23 100644 --- a/cpu.py +++ b/cpu.py @@ -190,69 +190,6 @@ class Fetch: self.output_instruction = Signal(32, name="fetch_ouutput_instruction") self.output_state = Signal(fetch_output_state,name="fetch_output_state") - def get_fetch_action(self, dc, load_store_misaligned, mi, - branch_taken, misaligned_jump_target, - csr_op_is_valid): - c = {} - c["default"] = self.action.eq(FA.default) # XXX should be 32'XXXXXXXX? - c[FOS.empty] = self.action.eq(FA.default) - c[FOS.trap] = self.action.eq(FA.ack_trap) - - # illegal instruction -> error trap - i= If((dc.act & DA.trap_illegal_instruction) != 0, - self.action.eq(FA.error_trap) - ) - - # ecall / ebreak -> noerror trap - i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0, - self.action.eq(FA.noerror_trap)) - - # load/store: check alignment, check wait - i = i.Elif((dc.act & (DA.load | DA.store)) != 0, - If((load_store_misaligned | ~mi.rw_address_valid), - self.action.eq(FA.error_trap) # misaligned or invalid addr - ).Elif(mi.rw_wait, - self.action.eq(FA.wait) # wait - ).Else( - self.action.eq(FA.default) # ok - ) - ) - - # fence - i = i.Elif((dc.act & DA.fence) != 0, - self.action.eq(FA.fence)) - - # branch -> misaligned=error, otherwise jump - i = i.Elif((dc.act & DA.branch) != 0, - If(misaligned_jump_target, - self.action.eq(FA.error_trap) - ).Else( - self.action.eq(FA.jump) - ) - ) - - # jal/jalr -> misaligned=error, otherwise jump - i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0, - If(misaligned_jump_target, - self.action.eq(FA.error_trap) - ).Else( - self.action.eq(FA.jump) - ) - ) - - # csr -> opvalid=ok, else error trap - i = i.Elif((dc.act & DA.csr) != 0, - If(csr_op_is_valid, - self.action.eq(FA.default) - ).Else( - self.action.eq(FA.error_trap) - ) - ) - - c[FOS.valid] = i - - return Case(self.output_state, c) - class CSR: def __init__(self, comb, sync, dc, register_rs1): self.comb = comb @@ -353,16 +290,6 @@ class CPU(Module): """ """ - def get_ls_misaligned(self, ls, funct3, load_store_address_low_2): - """ returns whether a load/store is misaligned - """ - return Case(funct3[:2], - { F3.sb: ls.eq(Constant(0)), - F3.sh: ls.eq(load_store_address_low_2[0] != 0), - F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)), - "default": ls.eq(Constant(1)) - }) - def get_lsbm(self, dc): return Cat(Constant(1), Mux((dc.funct3[1] | dc.funct3[0]), @@ -576,24 +503,6 @@ class CPU(Module): self.write_register(dc.rd, csr_output_value) )] - """ - `csr_mip: begin - csr_output_value = 0; - csr_output_value[11] = mip_meip; - csr_output_value[9] = mip_seip; - csr_output_value[8] = mip_ueip; - csr_output_value[7] = mip_mtip; - csr_output_value[5] = mip_stip; - csr_output_value[4] = mip_utip; - csr_output_value[3] = mip_msip; - csr_output_value[1] = mip_ssip; - csr_output_value[0] = mip_usip; - end - endcase - end - endcase - end - """ def __init__(self): Module.__init__(self) self.clk = ClockSignal() @@ -695,16 +604,23 @@ class CPU(Module): load_store_address = Signal(32) load_store_address_low_2 = Signal(2) - - self.comb += load_store_address.eq(dc.immediate + self.regs.rs1) - self.comb += load_store_address_low_2.eq( - dc.immediate[:2] + self.regs.rs1[:2]) - load_store_misaligned = Signal() + unmasked_loaded_value = Signal(32) + loaded_value = Signal(32) + + lsc = Instance("CPULoadStoreCalc", name="cpu_loadstore_calc", + i_dc_immediate = dc.immediate, + i_dc_funct3 = dc.funct3, + i_rs1 = self.regs.rs1, + i_rs2 = self.regs.rs2, + i_rw_data_in = mi.rw_data_in, + i_rw_data_out = mi.rw_data_out, + o_load_store_address = load_store_address, + o_load_store_address_low_2 = load_store_address_low_2, + o_load_store_misaligned = load_store_misaligned, + o_loaded_value = loaded_value) - lsa = self.get_ls_misaligned(load_store_misaligned, dc.funct3, - load_store_address_low_2) - self.comb += lsa + self.specials += lsc # XXX rwaddr not 31:2 any more self.comb += mi.rw_address.eq(load_store_address[2:]) @@ -719,50 +635,6 @@ class CPU(Module): _Operator("<<", [unshifted_load_store_byte_mask, load_store_address_low_2])) - # XXX not obvious - b3 = Mux(load_store_address_low_2[1], - Mux(load_store_address_low_2[0], self.regs.rs2[0:8], - self.regs.rs2[8:16]), - Mux(load_store_address_low_2[0], self.regs.rs2[16:24], - self.regs.rs2[24:32])) - b2 = Mux(load_store_address_low_2[1], self.regs.rs2[0:8], - self.regs.rs2[16:24]) - b1 = Mux(load_store_address_low_2[0], self.regs.rs2[0:8], - self.regs.rs2[8:16]) - b0 = self.regs.rs2[0:8] - - self.comb += mi.rw_data_in.eq(Cat(b0, b1, b2, b3)) - - # XXX not obvious - unmasked_loaded_value = Signal(32) - - b0 = Mux(load_store_address_low_2[1], - Mux(load_store_address_low_2[0], mi.rw_data_out[24:32], - mi.rw_data_out[16:24]), - Mux(load_store_address_low_2[0], mi.rw_data_out[15:8], - mi.rw_data_out[0:8])) - b1 = Mux(load_store_address_low_2[1], mi.rw_data_out[24:31], - mi.rw_data_out[8:16]) - b23 = mi.rw_data_out[16:32] - - self.comb += unmasked_loaded_value.eq(Cat(b0, b1, b23)) - - # XXX not obvious - loaded_value = Signal(32) - - b0 = unmasked_loaded_value[0:8] - b1 = Mux(dc.funct3[0:2] == 0, - Replicate(~dc.funct3[2] & unmasked_loaded_value[7], 8), - unmasked_loaded_value[8:16]) - b2 = Mux(dc.funct3[1] == 0, - Replicate(~dc.funct3[2] & - Mux(dc.funct3[0], unmasked_loaded_value[15], - unmasked_loaded_value[7]), - 16), - unmasked_loaded_value[16:32]) - - self.comb += loaded_value.eq(Cat(b0, b1, b2)) - self.comb += mi.rw_active.eq(~self.reset & (ft.output_state == FOS.valid) & ~load_store_misaligned @@ -825,9 +697,18 @@ class CPU(Module): # CSR decoding csr = CSR(self.comb, self.sync, dc, self.regs.rs1) - self.comb += ft.get_fetch_action(dc, load_store_misaligned, mi, - branch_taken, misaligned_jump_target, - csr.op_is_valid) + fi = Instance("CPUFetchAction", name="cpu_fetch_action", + o_fetch_action = ft.action, + i_output_state = ft.output_state, + i_dc_act = dc.act, + i_load_store_misaligned = load_store_misaligned, + i_mi_rw_wait = mi.rw_wait, + i_mi_rw_address_valid = mi.rw_address_valid, + i_branch_taken = branch_taken, + i_misaligned_jump_target = misaligned_jump_target, + i_csr_op_is_valid = csr.op_is_valid) + + self.specials += fi minfo = MInfo(self.comb)