X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=cpu.py;h=17172c9186b5e8e3e70f7c9bc35fdfe33a4a1bca;hb=a54966b8aca1fc5da8d3cb3a6ab1b7add4d9e146;hp=2f9d22b1af2b8bb4a83a5cdd0c849bbd45d47668;hpb=6662edc348905f57db369f5cb18654e099008d9c;p=rv32.git diff --git a/cpu.py b/cpu.py index 2f9d22b..17172c9 100644 --- a/cpu.py +++ b/cpu.py @@ -58,46 +58,18 @@ class Decoder: opcode = Signal(7, name="decoder_opcode") act = Signal(decode_action, name="decoder_action") + class MStatus: def __init__(self, comb, sync): self.comb = comb self.sync = sync self.mpie = Signal(name="mstatus_mpie") self.mie = Signal(name="mstatus_mie") - self.mprv = Signal(name="mstatus_mprv") - self.tsr = Signal(name="mstatus_tsr") - self.tw = Signal(name="mstatus_tw") - self.tvm = Signal(name="mstatus_tvm") - self.mxr = Signal(name="mstatus_mxr") - self._sum = Signal(name="mstatus_sum") - self.xs = Signal(name="mstatus_xs") - self.fs = Signal(name="mstatus_fs") - self.mpp = Signal(2, name="mstatus_mpp") - self.spp = Signal(name="mstatus_spp") - self.spie = Signal(name="mstatus_spie") - self.upie = Signal(name="mstatus_upie") - self.sie = Signal(name="mstatus_sie") - self.uie = Signal(name="mstatus_uie") - - for n in dir(self): - if n in ['make', 'mpp', 'comb', 'sync'] or n.startswith("_"): - continue - self.comb += getattr(self, n).eq(0x0) - self.comb += self.mpp.eq(0b11) + self.mstatus = Signal(32, name="mstatus") self.sync += self.mie.eq(0) self.sync += self.mpie.eq(0) - - def make(self): - return Cat( - self.uie, self.sie, Constant(0), self.mie, - self.upie, self.spie, Constant(0), self.mpie, - self.spp, Constant(0, 2), self.mpp, - self.fs, self.xs, self.mprv, self._sum, - self.mxr, self.tvm, self.tw, self.tsr, - Constant(0, 8), - (self.xs == Constant(0b11, 2)) | (self.fs == Constant(0b11, 2)) - ) + self.sync += self.mstatus.eq(0) class MIE: @@ -107,26 +79,7 @@ class MIE: self.meie = Signal(name="mie_meie") self.mtie = Signal(name="mie_mtie") self.msie = Signal(name="mie_msie") - self.seie = Signal(name="mie_seie") - self.ueie = Signal(name="mie_ueie") - self.stie = Signal(name="mie_stie") - self.utie = Signal(name="mie_utie") - self.ssie = Signal(name="mie_ssie") - self.usie = Signal(name="mie_usie") - - for n in dir(self): - if n in ['make', 'comb', 'sync'] or n.startswith("_"): - continue - self.comb += getattr(self, n).eq(0x0) - - self.sync += self.meie.eq(0) - self.sync += self.mtie.eq(0) - self.sync += self.msie.eq(0) - - def make(self): - return Cat( self.usie, self.ssie, 0, self.msie, - self.utie, self.stie, 0, self.mtie, - self.ueie, self.seie, 0, self.meie, ) + self.mie = Signal(32) class MIP: @@ -190,69 +143,6 @@ class Fetch: self.output_instruction = Signal(32, name="fetch_ouutput_instruction") self.output_state = Signal(fetch_output_state,name="fetch_output_state") - def get_fetch_action(self, dc, load_store_misaligned, mi, - branch_taken, misaligned_jump_target, - csr_op_is_valid): - c = {} - c["default"] = self.action.eq(FA.default) # XXX should be 32'XXXXXXXX? - c[FOS.empty] = self.action.eq(FA.default) - c[FOS.trap] = self.action.eq(FA.ack_trap) - - # illegal instruction -> error trap - i= If((dc.act & DA.trap_illegal_instruction) != 0, - self.action.eq(FA.error_trap) - ) - - # ecall / ebreak -> noerror trap - i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0, - self.action.eq(FA.noerror_trap)) - - # load/store: check alignment, check wait - i = i.Elif((dc.act & (DA.load | DA.store)) != 0, - If((load_store_misaligned | ~mi.rw_address_valid), - self.action.eq(FA.error_trap) # misaligned or invalid addr - ).Elif(mi.rw_wait, - self.action.eq(FA.wait) # wait - ).Else( - self.action.eq(FA.default) # ok - ) - ) - - # fence - i = i.Elif((dc.act & DA.fence) != 0, - self.action.eq(FA.fence)) - - # branch -> misaligned=error, otherwise jump - i = i.Elif((dc.act & DA.branch) != 0, - If(misaligned_jump_target, - self.action.eq(FA.error_trap) - ).Else( - self.action.eq(FA.jump) - ) - ) - - # jal/jalr -> misaligned=error, otherwise jump - i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0, - If(misaligned_jump_target, - self.action.eq(FA.error_trap) - ).Else( - self.action.eq(FA.jump) - ) - ) - - # csr -> opvalid=ok, else error trap - i = i.Elif((dc.act & DA.csr) != 0, - If(csr_op_is_valid, - self.action.eq(FA.default) - ).Else( - self.action.eq(FA.error_trap) - ) - ) - - c[FOS.valid] = i - - return Case(self.output_state, c) - class CSR: def __init__(self, comb, sync, dc, register_rs1): self.comb = comb @@ -337,32 +227,22 @@ class Regs: self.comb = comb self.sync = sync - self.ra_en = Signal(reset=1) - self.rb_en = Signal(reset=1) - self.wen = Signal(name="register_wen") + self.ra_en = Signal(reset=1, name="regfile_ra_en") # TODO: ondemand en + self.rs1 = Signal(32, name="regfile_rs1") + self.rs_a = Signal(5, name="regfile_rs_a") - self.rs1 = Signal(32, name="register_rs1") - self.rs2 = Signal(32, name="register_rs2") - self.wval = Signal(32, name="register_wval") + self.rb_en = Signal(reset=1, name="regfile_rb_en") # TODO: ondemand en + self.rs2 = Signal(32, name="regfile_rs2") + self.rs_b = Signal(5, name="regfile_rs_b") - self.rs_a = Signal(5, name="register_rs_a") - self.rs_b = Signal(5, name="register_rs_b") - self.rd = Signal(32, name="register_rd") + self.w_en = Signal(name="regfile_w_en") + self.wval = Signal(32, name="regfile_wval") + self.rd = Signal(32, name="regfile_rd") class CPU(Module): """ """ - def get_ls_misaligned(self, ls, funct3, load_store_address_low_2): - """ returns whether a load/store is misaligned - """ - return Case(funct3[:2], - { F3.sb: ls.eq(Constant(0)), - F3.sh: ls.eq(load_store_address_low_2[0] != 0), - F3.sw: ls.eq(load_store_address_low_2[0:2] != Constant(0, 2)), - "default": ls.eq(Constant(1)) - }) - def get_lsbm(self, dc): return Cat(Constant(1), Mux((dc.funct3[1] | dc.funct3[0]), @@ -443,7 +323,7 @@ class CPU(Module): def write_register(self, rd, val): return [self.regs.rd.eq(rd), self.regs.wval.eq(val), - self.regs.wen.eq(1) + self.regs.w_en.eq(1) ] def handle_valid(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie, @@ -455,7 +335,7 @@ class CPU(Module): i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap), [self.handle_trap(m, mstatus, ft, dc, load_store_misaligned), - self.regs.wen.eq(0) # no writing to registers + self.regs.w_en.eq(0) # no writing to registers ] ) @@ -490,7 +370,7 @@ class CPU(Module): i = i.Elif((dc.act & (DA.fence | DA.fence_i | DA.store | DA.branch)) != 0, # do nothing - self.regs.wen.eq(0) # no writing to registers + self.regs.w_en.eq(0) # no writing to registers ) return i @@ -518,7 +398,7 @@ class CPU(Module): c[csr_misa ] = csr_output_value.eq(misa.misa) # mstatus c[csr_mstatus ] = [ - csr_output_value.eq(mstatus.make()), + csr_output_value.eq(mstatus.mstatus), csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value, csr_written_value), mstatus.mpie.eq(csr_written_value[7]), @@ -526,7 +406,7 @@ class CPU(Module): ] # mie c[csr_mie ] = [ - csr_output_value.eq(mie.make()), + csr_output_value.eq(mie.mie), csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value, csr_written_value), mie.meie.eq(csr_written_value[11]), @@ -576,24 +456,6 @@ class CPU(Module): self.write_register(dc.rd, csr_output_value) )] - """ - `csr_mip: begin - csr_output_value = 0; - csr_output_value[11] = mip_meip; - csr_output_value[9] = mip_seip; - csr_output_value[8] = mip_ueip; - csr_output_value[7] = mip_mtip; - csr_output_value[5] = mip_stip; - csr_output_value[4] = mip_utip; - csr_output_value[3] = mip_msip; - csr_output_value[1] = mip_ssip; - csr_output_value[0] = mip_usip; - end - endcase - end - endcase - end - """ def __init__(self): Module.__init__(self) self.clk = ClockSignal() @@ -619,7 +481,7 @@ class CPU(Module): rf = Instance("RegFile", name="regfile", i_ra_en = self.regs.ra_en, i_rb_en = self.regs.rb_en, - i_w_en = self.regs.wen, + i_w_en = self.regs.w_en, o_read_a = self.regs.rs1, o_read_b = self.regs.rs2, i_writeval = self.regs.wval, @@ -695,16 +557,23 @@ class CPU(Module): load_store_address = Signal(32) load_store_address_low_2 = Signal(2) - - self.comb += load_store_address.eq(dc.immediate + self.regs.rs1) - self.comb += load_store_address_low_2.eq( - dc.immediate[:2] + self.regs.rs1[:2]) - load_store_misaligned = Signal() + unmasked_loaded_value = Signal(32) + loaded_value = Signal(32) - lsa = self.get_ls_misaligned(load_store_misaligned, dc.funct3, - load_store_address_low_2) - self.comb += lsa + lsc = Instance("CPULoadStoreCalc", name="cpu_loadstore_calc", + i_dc_immediate = dc.immediate, + i_dc_funct3 = dc.funct3, + i_rs1 = self.regs.rs1, + i_rs2 = self.regs.rs2, + i_rw_data_in = mi.rw_data_in, + i_rw_data_out = mi.rw_data_out, + o_load_store_address = load_store_address, + o_load_store_address_low_2 = load_store_address_low_2, + o_load_store_misaligned = load_store_misaligned, + o_loaded_value = loaded_value) + + self.specials += lsc # XXX rwaddr not 31:2 any more self.comb += mi.rw_address.eq(load_store_address[2:]) @@ -719,50 +588,6 @@ class CPU(Module): _Operator("<<", [unshifted_load_store_byte_mask, load_store_address_low_2])) - # XXX not obvious - b3 = Mux(load_store_address_low_2[1], - Mux(load_store_address_low_2[0], self.regs.rs2[0:8], - self.regs.rs2[8:16]), - Mux(load_store_address_low_2[0], self.regs.rs2[16:24], - self.regs.rs2[24:32])) - b2 = Mux(load_store_address_low_2[1], self.regs.rs2[0:8], - self.regs.rs2[16:24]) - b1 = Mux(load_store_address_low_2[0], self.regs.rs2[0:8], - self.regs.rs2[8:16]) - b0 = self.regs.rs2[0:8] - - self.comb += mi.rw_data_in.eq(Cat(b0, b1, b2, b3)) - - # XXX not obvious - unmasked_loaded_value = Signal(32) - - b0 = Mux(load_store_address_low_2[1], - Mux(load_store_address_low_2[0], mi.rw_data_out[24:32], - mi.rw_data_out[16:24]), - Mux(load_store_address_low_2[0], mi.rw_data_out[15:8], - mi.rw_data_out[0:8])) - b1 = Mux(load_store_address_low_2[1], mi.rw_data_out[24:31], - mi.rw_data_out[8:16]) - b23 = mi.rw_data_out[16:32] - - self.comb += unmasked_loaded_value.eq(Cat(b0, b1, b23)) - - # XXX not obvious - loaded_value = Signal(32) - - b0 = unmasked_loaded_value[0:8] - b1 = Mux(dc.funct3[0:2] == 0, - Replicate(~dc.funct3[2] & unmasked_loaded_value[7], 8), - unmasked_loaded_value[8:16]) - b2 = Mux(dc.funct3[1] == 0, - Replicate(~dc.funct3[2] & - Mux(dc.funct3[0], unmasked_loaded_value[15], - unmasked_loaded_value[7]), - 16), - unmasked_loaded_value[16:32]) - - self.comb += loaded_value.eq(Cat(b0, b1, b2)) - self.comb += mi.rw_active.eq(~self.reset & (ft.output_state == FOS.valid) & ~load_store_misaligned @@ -822,12 +647,36 @@ class CPU(Module): misa = Misa(self.comb, self.sync) mip = MIP(self.comb, self.sync) + mii = Instance("CPUMIE", name="cpu_mie", + o_mie = mie.mie, + i_meie = mie.meie, + i_mtie = mie.mtie, + i_msie = mie.msie) + + self.specials += mii + + ms = Instance("CPUMStatus", name="cpu_mstatus", + o_mstatus = mstatus.mstatus, + i_mpie = mstatus.mpie, + i_mie = mstatus.mie) + + self.specials += ms + # CSR decoding csr = CSR(self.comb, self.sync, dc, self.regs.rs1) - self.comb += ft.get_fetch_action(dc, load_store_misaligned, mi, - branch_taken, misaligned_jump_target, - csr.op_is_valid) + fi = Instance("CPUFetchAction", name="cpu_fetch_action", + o_fetch_action = ft.action, + i_output_state = ft.output_state, + i_dc_act = dc.act, + i_load_store_misaligned = load_store_misaligned, + i_mi_rw_wait = mi.rw_wait, + i_mi_rw_address_valid = mi.rw_address_valid, + i_branch_taken = branch_taken, + i_misaligned_jump_target = misaligned_jump_target, + i_csr_op_is_valid = csr.op_is_valid) + + self.specials += fi minfo = MInfo(self.comb)