X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=cpu.py;h=47985745841e156ea462c3f12b8066e511c8f791;hb=8125f6d7c3535e5c50b24399d45b7aa6d12154c7;hp=ae24ce42c81e2afada7088adc7ac43e30864ab8d;hpb=4085d7f10a044436f19b8b1ee4a26e36047499f1;p=rv32.git

diff --git a/cpu.py b/cpu.py
index ae24ce4..4798574 100644
--- a/cpu.py
+++ b/cpu.py
@@ -26,6 +26,7 @@
 `include "cpu.vh"
 """
 
+import string
 from migen import *
 from migen.fhdl import verilog
 from migen.fhdl.structure import _Operator
@@ -57,6 +58,115 @@ class Decoder:
     opcode = Signal(7, name="decoder_opcode")
     act = Signal(decode_action, name="decoder_action")
 
+class MStatus:
+    def __init__(self, comb, sync):
+        self.comb = comb
+        self.sync = sync
+        self.mpie = Signal(name="mstatus_mpie")
+        self.mie = Signal(name="mstatus_mie")
+        self.mprv = Signal(name="mstatus_mprv")
+        self.tsr = Signal(name="mstatus_tsr")
+        self.tw = Signal(name="mstatus_tw")
+        self.tvm = Signal(name="mstatus_tvm")
+        self.mxr = Signal(name="mstatus_mxr")
+        self._sum = Signal(name="mstatus_sum")
+        self.xs = Signal(name="mstatus_xs")
+        self.fs = Signal(name="mstatus_fs")
+        self.mpp = Signal(2, name="mstatus_mpp")
+        self.spp = Signal(name="mstatus_spp")
+        self.spie = Signal(name="mstatus_spie")
+        self.upie = Signal(name="mstatus_upie")
+        self.sie = Signal(name="mstatus_sie")
+        self.uie = Signal(name="mstatus_uie")
+
+        for n in dir(self):
+            if n in ['make', 'mpp', 'comb', 'sync'] or n.startswith("_"):
+                continue
+            self.comb += getattr(self, n).eq(0x0)
+        self.comb += self.mpp.eq(0b11)
+
+        self.sync += self.mie.eq(0)
+        self.sync += self.mpie.eq(0)
+
+    def make(self):
+        return Cat(
+                self.uie, self.sie, Constant(0), self.mie,
+                self.upie, self.spie, Constant(0), self.mpie,
+                self.spp, Constant(0, 2), self.mpp,
+                self.fs, self.xs, self.mprv, self._sum,
+                self.mxr, self.tvm, self.tw, self.tsr,
+                Constant(0, 8),
+                (self.xs == Constant(0b11, 2)) | (self.fs == Constant(0b11, 2))
+                )
+
+
+class MIE:
+    def __init__(self, comb, sync):
+        self.comb = comb
+        self.sync = sync
+        self.meie = Signal(name="mie_meie")
+        self.mtie = Signal(name="mie_mtie")
+        self.msie = Signal(name="mie_msie")
+        self.ueie = Signal(name="mie_ueie")
+        self.stie = Signal(name="mie_stie")
+        self.utie = Signal(name="mie_utie")
+        self.ssie = Signal(name="mie_ssie")
+        self.usie = Signal(name="mie_usie")
+
+        for n in dir(self):
+            if n in ['make', 'comb', 'sync'] or n.startswith("_"):
+                continue
+            self.comb += getattr(self, n).eq(0x0)
+
+        self.sync += self.meie.eq(0)
+        self.sync += self.mtie.eq(0)
+        self.sync += self.msie.eq(0)
+
+class MIP:
+    def __init__(self, comb, sync):
+        self.comb = comb
+        self.sync = sync
+        self.meip = Signal(name="mip_meip") # TODO: implement ext interrupts
+        self.seip = Signal(name="mip_seip")
+        self.ueip = Signal(name="mip_uiep")
+        self.mtip = Signal(name="mip_mtip") # TODO: implement timer interrupts
+        self.stip = Signal(name="mip_stip")
+        self.msip = Signal(name="mip_stip")
+        self.utip = Signal(name="mip_utip")
+        self.ssip = Signal(name="mip_ssip")
+        self.usip = Signal(name="mip_usip")
+
+        for n in dir(self):
+            if n in ['comb', 'sync'] or n.startswith("_"):
+                continue
+            self.comb += getattr(self, n).eq(0x0)
+
+
+class M:
+    def __init__(self, comb, sync):
+        self.comb = comb
+        self.sync = sync
+        self.mcause = Signal(32)
+        self.mepc = Signal(32)
+        self.mscratch = Signal(32)
+        self.sync += self.mcause.eq(0)
+        self.sync += self.mepc.eq(0) # 32'hXXXXXXXX;
+        self.sync += self.mscratch.eq(0) # 32'hXXXXXXXX;
+
+class Misa:
+
+    def __init__(self, comb, sync):
+        self.comb = comb
+        self.sync = sync
+        self.misa = Signal(32)
+        cl = []
+        for l in list(string.ascii_lowercase):
+            value = 1 if l == 'i' else 0
+            cl.append(Constant(value))
+        cl.append(Constant(0, 4))
+        cl.append(Constant(0b01, 2))
+        self.comb += self.misa.eq(Cat(cl))
+
 
 class CPU(Module):
     """
@@ -77,6 +187,99 @@ class CPU(Module):
                    Mux((dc.funct3[1]),
                        Constant(0b11, 2), Constant(0, 2)))
 
+    # XXX this happens to get done by various self.sync actions
+    #def reset_to_initial(self, m, mstatus, mie, registers):
+    #    return [m.mcause.eq(0),
+    #            ]
+
+    def write_register(self, register_number, value):
+        return If(register_number != 0,
+                  self.registers[register_number].eq(value)
+               )
+
+    def evaluate_csr_funct3_op(self, funct3, previous_value, written_value):
+        c = { "default": Constant(0, 32)}
+        for f in [F3.csrrw, F3.csrrwi]: c[f] = written_value
+        for f in [F3.csrrs, F3.csrrsi]: c[f] = written_value | previous_value
+        for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value
+        return Case(funct3, c)
+
+    """
+    def get_fetch_action(self, fetch_output_state,
+        input `decode_action decode_action,
+        input load_store_misaligned,
+        input memory_interface_rw_address_valid,
+        input memory_interface_rw_wait,
+        input branch_taken,
+        input misaligned_jump_target,
+        input csr_op_is_valid
+        );
+    begin
+        case(fetch_output_state)
+        `fetch_output_state_empty:
+            get_fetch_action = `fetch_action_default;
+        `fetch_output_state_trap:
+            get_fetch_action = `fetch_action_ack_trap;
+        `fetch_output_state_valid: begin
+            if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
+                get_fetch_action = `fetch_action_error_trap;
+            end
+            else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
+                get_fetch_action = `fetch_action_noerror_trap;
+            end
+            else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin
+                if(load_store_misaligned | ~memory_interface_rw_address_valid) begin
+                    get_fetch_action = `fetch_action_error_trap;
+                end
+                else if(memory_interface_rw_wait) begin
+                    get_fetch_action = `fetch_action_wait;
+                end
+                else begin
+                    get_fetch_action = `fetch_action_default;
+                end
+            end
+            else if((decode_action & `decode_action_fence_i) != 0) begin
+                get_fetch_action = `fetch_action_fence;
+            end
+            else if((decode_action & `decode_action_branch) != 0) begin
+                if(branch_taken) begin
+                    if(misaligned_jump_target) begin
+                        get_fetch_action = `fetch_action_error_trap;
+                    end
+                    else begin
+                        get_fetch_action = `fetch_action_jump;
+                    end
+                end
+                else
+                begin
+                    get_fetch_action = `fetch_action_default;
+                end
+            end
+            else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
+                if(misaligned_jump_target) begin
+                    get_fetch_action = `fetch_action_error_trap;
+                end
+                else begin
+                    get_fetch_action = `fetch_action_jump;
+                end
+            end
+            else if((decode_action & `decode_action_csr) != 0) begin
+                if(csr_op_is_valid)
+                    get_fetch_action = `fetch_action_default;
+                else
+                    get_fetch_action = `fetch_action_error_trap;
+            end
+            else begin
+                get_fetch_action = `fetch_action_default;
+            end
+        end
+        default:
+            get_fetch_action = 32'hXXXXXXXX;
+        endcase
+    end
+    endfunction
+    """
+
     def __init__(self):
         self.clk = ClockSignal()
         self.reset = ResetSignal()
@@ -98,8 +301,10 @@ class CPU(Module):
 
         l = []
         for i in range(31):
-            l.append(Signal(32, name="register%d" % i))
-        registers = Array(l)
+            r = Signal(32, name="register%d" % i)
+            l.append(r)
+            self.sync += r.eq(Constant(0, 32))
+        self.registers = Array(l)
 
         mi = MemoryInterface()
 
@@ -171,11 +376,11 @@ class CPU(Module):
         self.comb += If(dc.rs1 == 0,
                         register_rs1.eq(0)
                      ).Else(
-                        register_rs1.eq(registers[dc.rs1-1]))
+                        register_rs1.eq(self.registers[dc.rs1-1]))
         self.comb += If(dc.rs2 == 0,
                         register_rs2.eq(0)
                      ).Else(
-                        register_rs2.eq(registers[dc.rs2-1]))
+                        register_rs2.eq(self.registers[dc.rs2-1]))
 
         load_store_address = Signal(32)
         load_store_address_low_2 = Signal(2)
@@ -279,6 +484,46 @@ class CPU(Module):
                                              dc.immediate,
                                              dc.immediate + fetch_output_pc))
 
+        self.comb += fetch_target_pc.eq(Cat(0,
+                    Mux(dc.opcode != OP.jalr,
+                                fetch_output_pc[1:32],
+                                register_rs1[1:32] + dc.immediate[1:32])))
+
+        misaligned_jump_target = Signal()
+        self.comb += misaligned_jump_target.eq(fetch_target_pc[1])
+
+        branch_arg_a = Signal(32)
+        branch_arg_b = Signal(32)
+        self.comb += branch_arg_a.eq(Cat( register_rs1[0:31],
+                                          register_rs1[31] ^ ~dc.funct3[1]))
+        self.comb += branch_arg_b.eq(Cat( register_rs2[0:31],
+                                          register_rs2[31] ^ ~dc.funct3[1]))
+
+        branch_taken = Signal()
+        self.comb += branch_taken.eq(dc.funct3[0] ^
+                                     Mux(dc.funct3[2],
+                                         branch_arg_a < branch_arg_b,
+                                         branch_arg_a == branch_arg_b))
+
+        m = M(self.comb, self.sync)
+        mstatus = MStatus(self.comb, self.sync)
+        mie = MIE(self.comb, self.sync)
+
+        misa = Misa(self.comb, self.sync)
+
+        mvendorid = Signal(32)
+        marchid = Signal(32)
+        mimpid = Signal(32)
+        mhartid = Signal(32)
+        self.comb += mvendorid.eq(Constant(0, 32))
+        self.comb += marchid.eq(Constant(0, 32))
+        self.comb += mimpid.eq(Constant(0, 32))
+        self.comb += mhartid.eq(Constant(0, 32))
+
+        mip = MIP(self.comb, self.sync)
+
+        csr_op_is_valid = Signal()
+
 if __name__ == "__main__":
     example = CPU()
     print(verilog.convert(example,
@@ -294,229 +539,6 @@ if __name__ == "__main__":
 
 """
 
-    wire [31:0] lui_auipc_result = decoder_opcode[5] ? decoder_immediate : decoder_immediate + fetch_output_pc;
-
-    assign fetch_target_pc[31:1] = ((decoder_opcode != `opcode_jalr ? fetch_output_pc[31:1] : register_rs1[31:1]) + decoder_immediate[31:1]);
-    assign fetch_target_pc[0] = 0;
-
-    wire misaligned_jump_target = fetch_target_pc[1];
-
-    wire [31:0] branch_arg_a = {register_rs1[31] ^ ~decoder_funct3[1], register_rs1[30:0]};
-    wire [31:0] branch_arg_b = {register_rs2[31] ^ ~decoder_funct3[1], register_rs2[30:0]};
-
-    wire branch_taken = decoder_funct3[0] ^ (decoder_funct3[2] ? branch_arg_a < branch_arg_b : branch_arg_a == branch_arg_b);
-
-    reg [31:0] mcause = 0;
-    reg [31:0] mepc = 32'hXXXXXXXX;
-    reg [31:0] mscratch = 32'hXXXXXXXX;
-
-    reg mstatus_mpie = 1'bX;
-    reg mstatus_mie = 0;
-    parameter mstatus_mprv = 0;
-    parameter mstatus_tsr = 0;
-    parameter mstatus_tw = 0;
-    parameter mstatus_tvm = 0;
-    parameter mstatus_mxr = 0;
-    parameter mstatus_sum = 0;
-    parameter mstatus_xs = 0;
-    parameter mstatus_fs = 0;
-    parameter mstatus_mpp = 2'b11;
-    parameter mstatus_spp = 0;
-    parameter mstatus_spie = 0;
-    parameter mstatus_upie = 0;
-    parameter mstatus_sie = 0;
-    parameter mstatus_uie = 0;
-
-    reg mie_meie = 1'bX;
-    reg mie_mtie = 1'bX;
-    reg mie_msie = 1'bX;
-    parameter mie_seie = 0;
-    parameter mie_ueie = 0;
-    parameter mie_stie = 0;
-    parameter mie_utie = 0;
-    parameter mie_ssie = 0;
-    parameter mie_usie = 0;
-
-    task reset_to_initial;
-    begin
-        mcause = 0;
-        mepc = 32'hXXXXXXXX;
-        mscratch = 32'hXXXXXXXX;
-        mstatus_mie = 0;
-        mstatus_mpie = 1'bX;
-        mie_meie = 1'bX;
-        mie_mtie = 1'bX;
-        mie_msie = 1'bX;
-        registers['h01] <= 32'hXXXXXXXX;
-        registers['h02] <= 32'hXXXXXXXX;
-        registers['h03] <= 32'hXXXXXXXX;
-        registers['h04] <= 32'hXXXXXXXX;
-        registers['h05] <= 32'hXXXXXXXX;
-        registers['h06] <= 32'hXXXXXXXX;
-        registers['h07] <= 32'hXXXXXXXX;
-        registers['h08] <= 32'hXXXXXXXX;
-        registers['h09] <= 32'hXXXXXXXX;
-        registers['h0A] <= 32'hXXXXXXXX;
-        registers['h0B] <= 32'hXXXXXXXX;
-        registers['h0C] <= 32'hXXXXXXXX;
-        registers['h0D] <= 32'hXXXXXXXX;
-        registers['h0E] <= 32'hXXXXXXXX;
-        registers['h0F] <= 32'hXXXXXXXX;
-        registers['h10] <= 32'hXXXXXXXX;
-        registers['h11] <= 32'hXXXXXXXX;
-        registers['h12] <= 32'hXXXXXXXX;
-        registers['h13] <= 32'hXXXXXXXX;
-        registers['h14] <= 32'hXXXXXXXX;
-        registers['h15] <= 32'hXXXXXXXX;
-        registers['h16] <= 32'hXXXXXXXX;
-        registers['h17] <= 32'hXXXXXXXX;
-        registers['h18] <= 32'hXXXXXXXX;
-        registers['h19] <= 32'hXXXXXXXX;
-        registers['h1A] <= 32'hXXXXXXXX;
-        registers['h1B] <= 32'hXXXXXXXX;
-        registers['h1C] <= 32'hXXXXXXXX;
-        registers['h1D] <= 32'hXXXXXXXX;
-        registers['h1E] <= 32'hXXXXXXXX;
-        registers['h1F] <= 32'hXXXXXXXX;
-    end
-    endtask
-
-    task write_register(input [4:0] register_number, input [31:0] value);
-    begin
-        if(register_number != 0)
-            registers[register_number] <= value;
-    end
-    endtask
-
-    function [31:0] evaluate_csr_funct3_operation(input [2:0] funct3, input [31:0] previous_value, input [31:0] written_value);
-    begin
-        case(funct3)
-        `funct3_csrrw, `funct3_csrrwi:
-            evaluate_csr_funct3_operation = written_value;
-        `funct3_csrrs, `funct3_csrrsi:
-            evaluate_csr_funct3_operation = written_value | previous_value;
-        `funct3_csrrc, `funct3_csrrci:
-            evaluate_csr_funct3_operation = ~written_value & previous_value;
-        default:
-            evaluate_csr_funct3_operation = 32'hXXXXXXXX;
-        endcase
-    end
-    endfunction
-
-    parameter misa_a = 1'b0;
-    parameter misa_b = 1'b0;
-    parameter misa_c = 1'b0;
-    parameter misa_d = 1'b0;
-    parameter misa_e = 1'b0;
-    parameter misa_f = 1'b0;
-    parameter misa_g = 1'b0;
-    parameter misa_h = 1'b0;
-    parameter misa_i = 1'b1;
-    parameter misa_j = 1'b0;
-    parameter misa_k = 1'b0;
-    parameter misa_l = 1'b0;
-    parameter misa_m = 1'b0;
-    parameter misa_n = 1'b0;
-    parameter misa_o = 1'b0;
-    parameter misa_p = 1'b0;
-    parameter misa_q = 1'b0;
-    parameter misa_r = 1'b0;
-    parameter misa_s = 1'b0;
-    parameter misa_t = 1'b0;
-    parameter misa_u = 1'b0;
-    parameter misa_v = 1'b0;
-    parameter misa_w = 1'b0;
-    parameter misa_x = 1'b0;
-    parameter misa_y = 1'b0;
-    parameter misa_z = 1'b0;
-    parameter misa = {
-        2'b01,
-        4'b0,
-        misa_z,
-        misa_y,
-        misa_x,
-        misa_w,
-        misa_v,
-        misa_u,
-        misa_t,
-        misa_s,
-        misa_r,
-        misa_q,
-        misa_p,
-        misa_o,
-        misa_n,
-        misa_m,
-        misa_l,
-        misa_k,
-        misa_j,
-        misa_i,
-        misa_h,
-        misa_g,
-        misa_f,
-        misa_e,
-        misa_d,
-        misa_c,
-        misa_b,
-        misa_a};
-
-    parameter mvendorid = 32'b0;
-    parameter marchid = 32'b0;
-    parameter mimpid = 32'b0;
-    parameter mhartid = 32'b0;
-
-    function [31:0] make_mstatus(input mstatus_tsr,
-        input mstatus_tw,
-        input mstatus_tvm,
-        input mstatus_mxr,
-        input mstatus_sum,
-        input mstatus_mprv,
-        input [1:0] mstatus_xs,
-        input [1:0] mstatus_fs,
-        input [1:0] mstatus_mpp,
-        input mstatus_spp,
-        input mstatus_mpie,
-        input mstatus_spie,
-        input mstatus_upie,
-        input mstatus_mie,
-        input mstatus_sie,
-        input mstatus_uie);
-    begin
-        make_mstatus = {(mstatus_xs == 2'b11) | (mstatus_fs == 2'b11),
-            8'b0,
-            mstatus_tsr,
-            mstatus_tw,
-            mstatus_tvm,
-            mstatus_mxr,
-            mstatus_sum,
-            mstatus_mprv,
-            mstatus_xs,
-            mstatus_fs,
-            mstatus_mpp,
-            2'b0,
-            mstatus_spp,
-            mstatus_mpie,
-            1'b0,
-            mstatus_spie,
-            mstatus_upie,
-            mstatus_mie,
-            1'b0,
-            mstatus_sie,
-            mstatus_uie};
-    end
-    endfunction
-
-    wire mip_meip = 0; // TODO: implement external interrupts
-    parameter mip_seip = 0;
-    parameter mip_ueip = 0;
-    wire mip_mtip = 0; // TODO: implement timer interrupts
-    parameter mip_stip = 0;
-    parameter mip_utip = 0;
-    parameter mip_msip = 0;
-    parameter mip_ssip = 0;
-    parameter mip_usip = 0;
-
-    wire csr_op_is_valid;
-
     function `fetch_action get_fetch_action(
         input `fetch_output_state fetch_output_state,
         input `decode_action decode_action,