X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=cpu.py;h=5168a8793539b85d99c27b67516ca857afa093bf;hb=dfb0d060f5a9ebd70597e79de03f3675198f17e9;hp=d345a0099f8adec77bb4750a20af3c91e8378d54;hpb=a4647c592a6aa6c6fd85a790dc18811634dd1ded;p=rv32.git diff --git a/cpu.py b/cpu.py index d345a00..5168a87 100644 --- a/cpu.py +++ b/cpu.py @@ -153,6 +153,7 @@ class M: self.sync += self.mepc.eq(0) # 32'hXXXXXXXX; self.sync += self.mscratch.eq(0) # 32'hXXXXXXXX; + class Misa: def __init__(self, comb, sync): self.comb = comb @@ -177,12 +178,77 @@ class Fetch: self.output_instruction = Signal(32, name="fetch_ouutput_instruction") self.output_state = Signal(fetch_output_state,name="fetch_output_state") + def get_fetch_action(self, dc, load_store_misaligned, mi, + branch_taken, misaligned_jump_target, + csr_op_is_valid): + c = {} + c["default"] = self.action.eq(FA.default) # XXX should be 32'XXXXXXXX? + c[FOS.empty] = self.action.eq(FA.default) + c[FOS.trap] = self.action.eq(FA.ack_trap) + + # illegal instruction -> error trap + i= If((dc.act & DA.trap_illegal_instruction) != 0, + self.action.eq(FA.error_trap) + ) + + # ecall / ebreak -> noerror trap + i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0, + self.action.eq(FA.noerror_trap)) + + # load/store: check alignment, check wait + i = i.Elif((dc.act & (DA.load | DA.store)) != 0, + If((load_store_misaligned | ~mi.rw_address_valid), + self.action.eq(FA.error_trap) # misaligned or invalid addr + ).Elif(mi.rw_wait, + self.action.eq(FA.wait) # wait + ).Else( + self.action.eq(FA.default) # ok + ) + ) + + # fence + i = i.Elif((dc.act & DA.fence) != 0, + self.action.eq(FA.fence)) + + # branch -> misaligned=error, otherwise jump + i = i.Elif((dc.act & DA.branch) != 0, + If(misaligned_jump_target, + self.action.eq(FA.error_trap) + ).Else( + self.action.eq(FA.jump) + ) + ) + + # jal/jalr -> misaligned=error, otherwise jump + i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0, + If(misaligned_jump_target, + self.action.eq(FA.error_trap) + ).Else( + self.action.eq(FA.jump) + ) + ) + + # csr -> opvalid=ok, else error trap + i = i.Elif((dc.act & DA.csr) != 0, + If(csr_op_is_valid, + self.action.eq(FA.default) + ).Else( + self.action.eq(FA.error_trap) + ) + ) + + c[FOS.valid] = i + + return Case(self.output_state, c) + class CPU(Module): """ """ def get_ls_misaligned(self, ls, funct3, load_store_address_low_2): + """ returns whether a load/store is misaligned + """ return Case(funct3[:2], { F3.sb: ls.eq(Constant(0)), F3.sh: ls.eq(load_store_address_low_2[0] != 0), @@ -214,74 +280,41 @@ class CPU(Module): for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value return Case(funct3, c) - def get_fetch_action(self, ft, dc, load_store_misaligned, mi, - branch_taken, misaligned_jump_target, - csr_op_is_valid): - c = {} """ - case(fetch_output_state) - `fetch_output_state_empty: - get_fetch_action = `fetch_action_default; - `fetch_output_state_trap: - get_fetch_action = `fetch_action_ack_trap; - `fetch_output_state_valid: begin - if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin - get_fetch_action = `fetch_action_error_trap; - end - else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin - get_fetch_action = `fetch_action_noerror_trap; - end - else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin - if(load_store_misaligned | ~memory_interface_rw_address_valid) begin - get_fetch_action = `fetch_action_error_trap; - end - else if(memory_interface_rw_wait) begin - get_fetch_action = `fetch_action_wait; - end - else begin - get_fetch_action = `fetch_action_default; - end - end - else if((decode_action & `decode_action_fence_i) != 0) begin - get_fetch_action = `fetch_action_fence; - end - else if((decode_action & `decode_action_branch) != 0) begin - if(branch_taken) begin - if(misaligned_jump_target) begin - get_fetch_action = `fetch_action_error_trap; - end - else begin - get_fetch_action = `fetch_action_jump; - end - end - else - begin - get_fetch_action = `fetch_action_default; - end - end - else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin - if(misaligned_jump_target) begin - get_fetch_action = `fetch_action_error_trap; - end - else begin - get_fetch_action = `fetch_action_jump; - end - end - else if((decode_action & `decode_action_csr) != 0) begin - if(csr_op_is_valid) - get_fetch_action = `fetch_action_default; - else - get_fetch_action = `fetch_action_error_trap; - end - else begin - get_fetch_action = `fetch_action_default; - end + task handle_trap; + begin + mstatus_mpie = mstatus_mie; + mstatus_mie = 0; + mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc; + if(fetch_action == `fetch_action_ack_trap) begin + mcause = `cause_instruction_access_fault; + end + else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin + mcause = `cause_illegal_instruction; + end + else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin + mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint; + end + else if((decode_action & `decode_action_load) != 0) begin + if(load_store_misaligned) + mcause = `cause_load_address_misaligned; + else + mcause = `cause_load_access_fault; + end + else if((decode_action & `decode_action_store) != 0) begin + if(load_store_misaligned) + mcause = `cause_store_amo_address_misaligned; + else + mcause = `cause_store_amo_access_fault; + end + else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin + mcause = `cause_instruction_address_misaligned; + end + else begin + mcause = `cause_illegal_instruction; end - default: - get_fetch_action = 32'hXXXXXXXX; - endcase end - endfunction + endtask """ def __init__(self): @@ -453,7 +486,7 @@ class CPU(Module): self.comb += loaded_value.eq(Cat(b0, b1, b2)) self.comb += mi.rw_active.eq(~self.reset - & (ft.output_state == fetch_output_state_valid) + & (ft.output_state == FOS.valid) & ~load_store_misaligned & ((dc.act & (DA.load | DA.store)) != 0)) @@ -524,6 +557,9 @@ class CPU(Module): csr_op_is_valid = Signal() + self.comb += ft.get_fetch_action(dc, load_store_misaligned, mi, + branch_taken, misaligned_jump_target, + csr_op_is_valid) if __name__ == "__main__": example = CPU() print(verilog.convert(example, @@ -539,92 +575,6 @@ if __name__ == "__main__": """ - function `fetch_action get_fetch_action( - input `fetch_output_state fetch_output_state, - input `decode_action decode_action, - input load_store_misaligned, - input memory_interface_rw_address_valid, - input memory_interface_rw_wait, - input branch_taken, - input misaligned_jump_target, - input csr_op_is_valid - ); - begin - case(fetch_output_state) - `fetch_output_state_empty: - get_fetch_action = `fetch_action_default; - `fetch_output_state_trap: - get_fetch_action = `fetch_action_ack_trap; - `fetch_output_state_valid: begin - if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin - get_fetch_action = `fetch_action_error_trap; - end - else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin - get_fetch_action = `fetch_action_noerror_trap; - end - else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin - if(load_store_misaligned | ~memory_interface_rw_address_valid) begin - get_fetch_action = `fetch_action_error_trap; - end - else if(memory_interface_rw_wait) begin - get_fetch_action = `fetch_action_wait; - end - else begin - get_fetch_action = `fetch_action_default; - end - end - else if((decode_action & `decode_action_fence_i) != 0) begin - get_fetch_action = `fetch_action_fence; - end - else if((decode_action & `decode_action_branch) != 0) begin - if(branch_taken) begin - if(misaligned_jump_target) begin - get_fetch_action = `fetch_action_error_trap; - end - else begin - get_fetch_action = `fetch_action_jump; - end - end - else - begin - get_fetch_action = `fetch_action_default; - end - end - else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin - if(misaligned_jump_target) begin - get_fetch_action = `fetch_action_error_trap; - end - else begin - get_fetch_action = `fetch_action_jump; - end - end - else if((decode_action & `decode_action_csr) != 0) begin - if(csr_op_is_valid) - get_fetch_action = `fetch_action_default; - else - get_fetch_action = `fetch_action_error_trap; - end - else begin - get_fetch_action = `fetch_action_default; - end - end - default: - get_fetch_action = 32'hXXXXXXXX; - endcase - end - endfunction - - assign fetch_action = get_fetch_action( - fetch_output_state, - decode_action, - load_store_misaligned, - memory_interface_rw_address_valid, - memory_interface_rw_wait, - branch_taken, - misaligned_jump_target, - csr_op_is_valid - ); - task handle_trap; begin mstatus_mpie = mstatus_mie;