X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=cpu.py;h=9d50e5936e57137fd44f7719b4874b7738853ed7;hb=b0d897238492346241e62d168ac7ca57ea3e14b1;hp=4fbeafe61938fff05d0a6994e6240b4dd9705966;hpb=23bad0712788e3fbb2dc7767628456297aeac4ef;p=rv32.git diff --git a/cpu.py b/cpu.py index 4fbeafe..9d50e59 100644 --- a/cpu.py +++ b/cpu.py @@ -80,7 +80,7 @@ class MStatus: self.uie = Signal(name="mstatus_uie") for n in dir(self): - if n in ['mpp', 'comb', 'sync'] or n.startswith("_"): + if n in ['make', 'mpp', 'comb', 'sync'] or n.startswith("_"): continue self.comb += getattr(self, n).eq(0x0) self.comb += self.mpp.eq(0b11) @@ -88,6 +88,18 @@ class MStatus: self.sync += self.mie.eq(0) self.sync += self.mpie.eq(0) + def make(self): + return Cat( + self.uie, self.sie, Constant(0), self.mie, + self.upie, self.spie, Constant(0), self.mpie, + self.spp, Constant(0, 2), self.mpp, + self.fs, self.xs, self.mprv, self._sum, + self.mxr, self.tvm, self.tw, self.tsr, + Constant(0, 8), + (self.xs == Constant(0b11, 2)) | (self.fs == Constant(0b11, 2)) + ) + + class MIE: def __init__(self, comb, sync): self.comb = comb @@ -102,7 +114,7 @@ class MIE: self.usie = Signal(name="mie_usie") for n in dir(self): - if n in ['comb', 'sync'] or n.startswith("_"): + if n in ['make', 'comb', 'sync'] or n.startswith("_"): continue self.comb += getattr(self, n).eq(0x0) @@ -110,6 +122,25 @@ class MIE: self.sync += self.mtie.eq(0) self.sync += self.msie.eq(0) +class MIP: + def __init__(self, comb, sync): + self.comb = comb + self.sync = sync + self.meip = Signal(name="mip_meip") # TODO: implement ext interrupts + self.seip = Signal(name="mip_seip") + self.ueip = Signal(name="mip_uiep") + self.mtip = Signal(name="mip_mtip") # TODO: implement timer interrupts + self.stip = Signal(name="mip_stip") + self.msip = Signal(name="mip_stip") + self.utip = Signal(name="mip_utip") + self.ssip = Signal(name="mip_ssip") + self.usip = Signal(name="mip_usip") + + for n in dir(self): + if n in ['comb', 'sync'] or n.startswith("_"): + continue + self.comb += getattr(self, n).eq(0x0) + class M: def __init__(self, comb, sync): @@ -122,8 +153,8 @@ class M: self.sync += self.mepc.eq(0) # 32'hXXXXXXXX; self.sync += self.mscratch.eq(0) # 32'hXXXXXXXX; -class Misa: +class Misa: def __init__(self, comb, sync): self.comb = comb self.sync = sync @@ -137,11 +168,163 @@ class Misa: self.comb += self.misa.eq(Cat(cl)) +class Fetch: + def __init__(self, comb, sync): + self.comb = comb + self.sync = sync + self.action = Signal(fetch_action, name="fetch_action") + self.target_pc = Signal(32, name="fetch_target_pc") + self.output_pc = Signal(32, name="fetch_output_pc") + self.output_instruction = Signal(32, name="fetch_ouutput_instruction") + self.output_state = Signal(fetch_output_state,name="fetch_output_state") + + def get_fetch_action(self, dc, load_store_misaligned, mi, + branch_taken, misaligned_jump_target, + csr_op_is_valid): + c = {} + c["default"] = self.action.eq(FA.default) # XXX should be 32'XXXXXXXX? + c[FOS.empty] = self.action.eq(FA.default) + c[FOS.trap] = self.action.eq(FA.ack_trap) + + # illegal instruction -> error trap + i= If((dc.act & DA.trap_illegal_instruction) != 0, + self.action.eq(FA.error_trap) + ) + + # ecall / ebreak -> noerror trap + i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0, + self.action.eq(FA.noerror_trap)) + + # load/store: check alignment, check wait + i = i.Elif((dc.act & (DA.load | DA.store)) != 0, + If((load_store_misaligned | ~mi.rw_address_valid), + self.action.eq(FA.error_trap) # misaligned or invalid addr + ).Elif(mi.rw_wait, + self.action.eq(FA.wait) # wait + ).Else( + self.action.eq(FA.default) # ok + ) + ) + + # fence + i = i.Elif((dc.act & DA.fence) != 0, + self.action.eq(FA.fence)) + + # branch -> misaligned=error, otherwise jump + i = i.Elif((dc.act & DA.branch) != 0, + If(misaligned_jump_target, + self.action.eq(FA.error_trap) + ).Else( + self.action.eq(FA.jump) + ) + ) + + # jal/jalr -> misaligned=error, otherwise jump + i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0, + If(misaligned_jump_target, + self.action.eq(FA.error_trap) + ).Else( + self.action.eq(FA.jump) + ) + ) + + # csr -> opvalid=ok, else error trap + i = i.Elif((dc.act & DA.csr) != 0, + If(csr_op_is_valid, + self.action.eq(FA.default) + ).Else( + self.action.eq(FA.error_trap) + ) + ) + + c[FOS.valid] = i + + return Case(self.output_state, c) + +class CSR: + def __init__(self, comb, sync, dc, register_rs1): + self.comb = comb + self.sync = sync + self.number = Signal(12, name="csr_number") + self.input_value = Signal(32, name="csr_input_value") + self.reads = Signal(name="csr_reads") + self.writes = Signal(name="csr_writes") + self.op_is_valid = Signal(name="csr_op_is_valid") + + self.comb += self.number.eq(dc.immediate) + self.comb += self.input_value.eq(Mux(dc.funct3[2], + dc.rs1, + register_rs1)) + self.comb += self.reads.eq(dc.funct3[1] | (dc.rd != 0)) + self.comb += self.writes.eq(~dc.funct3[1] | (dc.rs1 != 0)) + + self.comb += self.get_csr_op_is_valid() + + def get_csr_op_is_valid(self): + """ determines if a CSR is valid + """ + c = {} + # invalid csrs + for f in [csr_ustatus, csr_fflags, csr_frm, csr_fcsr, + csr_uie, csr_utvec, csr_uscratch, csr_uepc, + csr_ucause, csr_utval, csr_uip, csr_sstatus, + csr_sedeleg, csr_sideleg, csr_sie, csr_stvec, + csr_scounteren, csr_sscratch, csr_sepc, csr_scause, + csr_stval, csr_sip, csr_satp, csr_medeleg, + csr_mideleg, csr_dcsr, csr_dpc, csr_dscratch]: + c[f] = self.op_is_valid.eq(0) + + # not-writeable -> ok + for f in [csr_cycle, csr_time, csr_instret, csr_cycleh, + csr_timeh, csr_instreth, csr_mvendorid, csr_marchid, + csr_mimpid, csr_mhartid]: + c[f] = self.op_is_valid.eq(~self.writes) + + # valid csrs + for f in [csr_misa, csr_mstatus, csr_mie, csr_mtvec, + csr_mscratch, csr_mepc, csr_mcause, csr_mip]: + c[f] = self.op_is_valid.eq(1) + + # not implemented / default + for f in [csr_mcounteren, csr_mtval, csr_mcycle, csr_minstret, + csr_mcycleh, csr_minstreth, "default"]: + c[f] = self.op_is_valid.eq(0) + + return Case(self.number, c) + + def evaluate_csr_funct3_op(self, funct3, previous_value, written_value): + c = { "default": Constant(0, 32)} + for f in [F3.csrrw, F3.csrrwi]: c[f] = written_value + for f in [F3.csrrs, F3.csrrsi]: c[f] = written_value | previous_value + for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value + return Case(funct3, c) + + +class MInfo: + def __init__(self, comb): + self.comb = comb + # TODO + self.cycle_counter = Signal(64); # TODO: implement cycle_counter + self.time_counter = Signal(64); # TODO: implement time_counter + self.instret_counter = Signal(64); # TODO: implement instret_counter + + self.mvendorid = Signal(32) + self.marchid = Signal(32) + self.mimpid = Signal(32) + self.mhartid = Signal(32) + self.comb += self.mvendorid.eq(Constant(0, 32)) + self.comb += self.marchid.eq(Constant(0, 32)) + self.comb += self.mimpid.eq(Constant(0, 32)) + self.comb += self.mhartid.eq(Constant(0, 32)) + + class CPU(Module): """ """ def get_ls_misaligned(self, ls, funct3, load_store_address_low_2): + """ returns whether a load/store is misaligned + """ return Case(funct3[:2], { F3.sb: ls.eq(Constant(0)), F3.sh: ls.eq(load_store_address_low_2[0] != 0), @@ -166,13 +349,241 @@ class CPU(Module): self.registers[register_number].eq(value) ) - def evaluate_csr_funct3_op(self, funct3, previous_value, written_value): - c = { "default": Constant(0, 32)} - for f in [F3.csrrw, F3.csrrwi]: c[f] = written_value - for f in [F3.csrrs, F3.csrrsi]: c[f] = written_value | previous_value - for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value - return Case(funct3, c) - + def handle_trap(self, m, ms, ft, dc, load_store_misaligned): + s = [ms.mpie.eq(ms.mie), + ms.mie.eq(0), + m.mepc.eq(Mux(ft.action == FA.noerror_trap, + ft.output_pc + 4, + ft.output_pc))] + + # fetch action ack trap + i = If(ft.action == FA.ack_trap, + m.mcause.eq(cause_instruction_access_fault) + ) + + # ecall/ebreak + i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0, + m.mcause.eq(Mux(dc.immediate[0], + cause_machine_environment_call, + cause_breakpoint)) + ) + + # load + i = i.Elif((dc.act & DA.load) != 0, + If(load_store_misaligned, + m.mcause.eq(cause_load_address_misaligned) + ).Else( + m.mcause.eq(cause_load_access_fault) + ) + ) + + # store + i = i.Elif((dc.act & DA.store) != 0, + If(load_store_misaligned, + m.mcause.eq(cause_store_amo_address_misaligned) + ).Else( + m.mcause.eq(cause_store_amo_access_fault) + ) + ) + + # jal/jalr -> misaligned=error, otherwise jump + i = i.Elif((dc.act & (DA.jal | DA.jalr | DA.branch)) != 0, + m.mcause.eq(cause_instruction_address_misaligned) + ) + + # defaults to illegal instruction + i = i.Else(m.mcause.eq(cause_illegal_instruction)) + + s.append(i) + return s + + def main_block(self, minfo, csr, mi, m, mstatus, ft, dc, + load_store_misaligned, + loaded_value, alu_result, + lui_auipc_result): + c = {} + c[FOS.empty] = [] + c[FOS.trap] = self.handle_trap(m, mstatus, ft, dc, + load_store_misaligned) + c[FOS.valid] = self.handle_valid(minfo, csr, mi, m, mstatus, ft, dc, + load_store_misaligned, + loaded_value, + alu_result, + lui_auipc_result) + return Case(ft.output_state, c) + + def handle_valid(self, minfo, csr, mi, m, mstatus, ft, dc, + load_store_misaligned, + loaded_value, alu_result, + lui_auipc_result): + # fetch action ack trap + i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap), + self.handle_trap(m, mstatus, ft, dc, + load_store_misaligned) + ) + + # load + i = i.Elif((dc.act & DA.load) != 0, + If(~mi.rw_wait, + self.write_register(dc.rd, loaded_value) + ) + ) + + # op or op_immediate + i = i.Elif((dc.act & DA.op_op_imm) != 0, + self.write_register(dc.rd, alu_result) + ) + + # lui or auipc + i = i.Elif((dc.act & DA.lui_auipc) != 0, + self.write_register(dc.rd, lui_auipc_result) + ) + + # jal/jalr + i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0, + self.write_register(dc.rd, ft.output_pc + 4) + ) + + i = i.Elif((dc.act & DA.csr) != 0, + self.handle_csr(minfo, mstatus, dc, csr) + ) + + # fence, store, branch + i = i.Elif((dc.act & (DA.fence | DA.fence_i | + DA.store | DA.branch)) != 0, + # do nothing + ) + + return i + + def handle_csr(self, minfo, mstatus, dc, csr): + csr_output_value = Signal() + csr_written_value = Signal() + c = {} + + return Case(csr.number, c) + + """ + reg [31:0] csr_output_value; + reg [31:0] csr_written_value; + csr_output_value = 32'hXXXXXXXX; + csr_written_value = 32'hXXXXXXXX; + case(csr_number) + `csr_cycle: begin + csr_output_value = cycle_counter[31:0]; + end + `csr_time: begin + csr_output_value = time_counter[31:0]; + end + `csr_instret: begin + csr_output_value = instret_counter[31:0]; + end + `csr_cycleh: begin + csr_output_value = cycle_counter[63:32]; + end + `csr_timeh: begin + csr_output_value = time_counter[63:32]; + end + `csr_instreth: begin + csr_output_value = instret_counter[63:32]; + end + `csr_mvendorid: begin + csr_output_value = mvendorid; + end + `csr_marchid: begin + csr_output_value = marchid; + end + `csr_mimpid: begin + csr_output_value = mimpid; + end + `csr_mhartid: begin + csr_output_value = mhartid; + end + `csr_misa: begin + csr_output_value = misa; + end + `csr_mstatus: begin + csr_output_value = make_mstatus(mstatus_tsr, + mstatus_tw, + mstatus_tvm, + mstatus_mxr, + mstatus_sum, + mstatus_mprv, + mstatus_xs, + mstatus_fs, + mstatus_mpp, + mstatus_spp, + mstatus_mpie, + mstatus_spie, + mstatus_upie, + mstatus_mie, + mstatus_sie, + mstatus_uie); + csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value); + if(csr_writes) begin + mstatus_mpie = csr_written_value[7]; + mstatus_mie = csr_written_value[3]; + end + end + `csr_mie: begin + csr_output_value = 0; + csr_output_value[11] = mie_meie; + csr_output_value[9] = mie_seie; + csr_output_value[8] = mie_ueie; + csr_output_value[7] = mie_mtie; + csr_output_value[5] = mie_stie; + csr_output_value[4] = mie_utie; + csr_output_value[3] = mie_msie; + csr_output_value[1] = mie_ssie; + csr_output_value[0] = mie_usie; + csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value); + if(csr_writes) begin + mie_meie = csr_written_value[11]; + mie_mtie = csr_written_value[7]; + mie_msie = csr_written_value[3]; + end + end + `csr_mtvec: begin + csr_output_value = mtvec; + end + `csr_mscratch: begin + csr_output_value = mscratch; + csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value); + if(csr_writes) + mscratch = csr_written_value; + end + `csr_mepc: begin + csr_output_value = mepc; + csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value); + if(csr_writes) + mepc = csr_written_value; + end + `csr_mcause: begin + csr_output_value = mcause; + csr_written_value = evaluate_csr_funct3_operation(decoder_funct3, csr_output_value, csr_input_value); + if(csr_writes) + mcause = csr_written_value; + end + `csr_mip: begin + csr_output_value = 0; + csr_output_value[11] = mip_meip; + csr_output_value[9] = mip_seip; + csr_output_value[8] = mip_ueip; + csr_output_value[7] = mip_mtip; + csr_output_value[5] = mip_stip; + csr_output_value[4] = mip_utip; + csr_output_value[3] = mip_msip; + csr_output_value[1] = mip_ssip; + csr_output_value[0] = mip_usip; + end + endcase + if(csr_reads) + write_register(decoder_rd, csr_output_value); + end + end + endcase + end + """ def __init__(self): self.clk = ClockSignal() self.reset = ResetSignal() @@ -227,11 +638,7 @@ class CPU(Module): ) self.specials += mii - fetch_act = Signal(fetch_action) - fetch_target_pc = Signal(32) - fetch_output_pc = Signal(32) - fetch_output_instruction = Signal(32) - fetch_output_st = Signal(fetch_output_state) + ft = Fetch(self.comb, self.sync) fs = Instance("CPUFetchStage", name="fetch_stage", i_clk=ClockSignal(), @@ -239,11 +646,11 @@ class CPU(Module): o_memory_interface_fetch_address = mi.fetch_address, i_memory_interface_fetch_data = mi.fetch_data, i_memory_interface_fetch_valid = mi.fetch_valid, - i_fetch_action = fetch_act, - i_target_pc = fetch_target_pc, - o_output_pc = fetch_output_pc, - o_output_instruction = fetch_output_instruction, - o_output_state = fetch_output_st, + i_fetch_action = ft.action, + i_target_pc = ft.target_pc, + o_output_pc = ft.output_pc, + o_output_instruction = ft.output_instruction, + o_output_state = ft.output_state, i_reset_vector = reset_vector, i_mtvec = mtvec, ) @@ -252,7 +659,7 @@ class CPU(Module): dc = Decoder() cd = Instance("CPUDecoder", name="decoder", - i_instruction = fetch_output_instruction, + i_instruction = ft.output_instruction, o_funct7 = dc.funct7, o_funct3 = dc.funct3, o_rd = dc.rd, @@ -346,7 +753,7 @@ class CPU(Module): self.comb += loaded_value.eq(Cat(b0, b1, b2)) self.comb += mi.rw_active.eq(~self.reset - & (fetch_output_st == fetch_output_state_valid) + & (ft.output_state == FOS.valid) & ~load_store_misaligned & ((dc.act & (DA.load | DA.store)) != 0)) @@ -375,15 +782,15 @@ class CPU(Module): lui_auipc_result = Signal(32) self.comb += lui_auipc_result.eq(Mux(dc.opcode[5], dc.immediate, - dc.immediate + fetch_output_pc)) + dc.immediate + ft.output_pc)) - self.comb += fetch_target_pc.eq(Cat(0, + self.comb += ft.target_pc.eq(Cat(0, Mux(dc.opcode != OP.jalr, - fetch_output_pc[1:32], + ft.output_pc[1:32], register_rs1[1:32] + dc.immediate[1:32]))) misaligned_jump_target = Signal() - self.comb += misaligned_jump_target.eq(fetch_target_pc[1]) + self.comb += misaligned_jump_target.eq(ft.target_pc[1]) branch_arg_a = Signal(32) branch_arg_b = Signal(32) @@ -401,11 +808,25 @@ class CPU(Module): m = M(self.comb, self.sync) mstatus = MStatus(self.comb, self.sync) mie = MIE(self.comb, self.sync) - misa = Misa(self.comb, self.sync) + mip = MIP(self.comb, self.sync) + + # CSR decoding + csr = CSR(self.comb, self.sync, dc, register_rs1) + + self.comb += ft.get_fetch_action(dc, load_store_misaligned, mi, + branch_taken, misaligned_jump_target, + csr.op_is_valid) + + minfo = MInfo(self.comb) - #self.sync += If(self.reset, self.reset_to_initial(m, mstatus, mie, - # registers)) + self.sync += If(~self.reset, + self.main_block(minfo, csr, mi, m, mstatus, ft, dc, + load_store_misaligned, + loaded_value, + alu_result, + lui_auipc_result) + ) if __name__ == "__main__": example = CPU() @@ -422,260 +843,6 @@ if __name__ == "__main__": """ - parameter mvendorid = 32'b0; - parameter marchid = 32'b0; - parameter mimpid = 32'b0; - parameter mhartid = 32'b0; - - function [31:0] make_mstatus(input mstatus_tsr, - input mstatus_tw, - input mstatus_tvm, - input mstatus_mxr, - input mstatus_sum, - input mstatus_mprv, - input [1:0] mstatus_xs, - input [1:0] mstatus_fs, - input [1:0] mstatus_mpp, - input mstatus_spp, - input mstatus_mpie, - input mstatus_spie, - input mstatus_upie, - input mstatus_mie, - input mstatus_sie, - input mstatus_uie); - begin - make_mstatus = {(mstatus_xs == 2'b11) | (mstatus_fs == 2'b11), - 8'b0, - mstatus_tsr, - mstatus_tw, - mstatus_tvm, - mstatus_mxr, - mstatus_sum, - mstatus_mprv, - mstatus_xs, - mstatus_fs, - mstatus_mpp, - 2'b0, - mstatus_spp, - mstatus_mpie, - 1'b0, - mstatus_spie, - mstatus_upie, - mstatus_mie, - 1'b0, - mstatus_sie, - mstatus_uie}; - end - endfunction - - wire mip_meip = 0; // TODO: implement external interrupts - parameter mip_seip = 0; - parameter mip_ueip = 0; - wire mip_mtip = 0; // TODO: implement timer interrupts - parameter mip_stip = 0; - parameter mip_utip = 0; - parameter mip_msip = 0; - parameter mip_ssip = 0; - parameter mip_usip = 0; - - wire csr_op_is_valid; - - function `fetch_action get_fetch_action( - input `fetch_output_state fetch_output_state, - input `decode_action decode_action, - input load_store_misaligned, - input memory_interface_rw_address_valid, - input memory_interface_rw_wait, - input branch_taken, - input misaligned_jump_target, - input csr_op_is_valid - ); - begin - case(fetch_output_state) - `fetch_output_state_empty: - get_fetch_action = `fetch_action_default; - `fetch_output_state_trap: - get_fetch_action = `fetch_action_ack_trap; - `fetch_output_state_valid: begin - if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin - get_fetch_action = `fetch_action_error_trap; - end - else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin - get_fetch_action = `fetch_action_noerror_trap; - end - else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin - if(load_store_misaligned | ~memory_interface_rw_address_valid) begin - get_fetch_action = `fetch_action_error_trap; - end - else if(memory_interface_rw_wait) begin - get_fetch_action = `fetch_action_wait; - end - else begin - get_fetch_action = `fetch_action_default; - end - end - else if((decode_action & `decode_action_fence_i) != 0) begin - get_fetch_action = `fetch_action_fence; - end - else if((decode_action & `decode_action_branch) != 0) begin - if(branch_taken) begin - if(misaligned_jump_target) begin - get_fetch_action = `fetch_action_error_trap; - end - else begin - get_fetch_action = `fetch_action_jump; - end - end - else - begin - get_fetch_action = `fetch_action_default; - end - end - else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin - if(misaligned_jump_target) begin - get_fetch_action = `fetch_action_error_trap; - end - else begin - get_fetch_action = `fetch_action_jump; - end - end - else if((decode_action & `decode_action_csr) != 0) begin - if(csr_op_is_valid) - get_fetch_action = `fetch_action_default; - else - get_fetch_action = `fetch_action_error_trap; - end - else begin - get_fetch_action = `fetch_action_default; - end - end - default: - get_fetch_action = 32'hXXXXXXXX; - endcase - end - endfunction - - assign fetch_action = get_fetch_action( - fetch_output_state, - decode_action, - load_store_misaligned, - memory_interface_rw_address_valid, - memory_interface_rw_wait, - branch_taken, - misaligned_jump_target, - csr_op_is_valid - ); - - task handle_trap; - begin - mstatus_mpie = mstatus_mie; - mstatus_mie = 0; - mepc = (fetch_action == `fetch_action_noerror_trap) ? fetch_output_pc + 4 : fetch_output_pc; - if(fetch_action == `fetch_action_ack_trap) begin - mcause = `cause_instruction_access_fault; - end - else if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin - mcause = `cause_illegal_instruction; - end - else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin - mcause = decoder_immediate[0] ? `cause_machine_environment_call : `cause_breakpoint; - end - else if((decode_action & `decode_action_load) != 0) begin - if(load_store_misaligned) - mcause = `cause_load_address_misaligned; - else - mcause = `cause_load_access_fault; - end - else if((decode_action & `decode_action_store) != 0) begin - if(load_store_misaligned) - mcause = `cause_store_amo_address_misaligned; - else - mcause = `cause_store_amo_access_fault; - end - else if((decode_action & (`decode_action_branch | `decode_action_jal | `decode_action_jalr)) != 0) begin - mcause = `cause_instruction_address_misaligned; - end - else begin - mcause = `cause_illegal_instruction; - end - end - endtask - - wire [11:0] csr_number = decoder_immediate; - wire [31:0] csr_input_value = decoder_funct3[2] ? decoder_rs1 : register_rs1; - wire csr_reads = decoder_funct3[1] | (decoder_rd != 0); - wire csr_writes = ~decoder_funct3[1] | (decoder_rs1 != 0); - - function get_csr_op_is_valid(input [11:0] csr_number, input csr_reads, input csr_writes); - begin - case(csr_number) - `csr_ustatus, - `csr_fflags, - `csr_frm, - `csr_fcsr, - `csr_uie, - `csr_utvec, - `csr_uscratch, - `csr_uepc, - `csr_ucause, - `csr_utval, - `csr_uip, - `csr_sstatus, - `csr_sedeleg, - `csr_sideleg, - `csr_sie, - `csr_stvec, - `csr_scounteren, - `csr_sscratch, - `csr_sepc, - `csr_scause, - `csr_stval, - `csr_sip, - `csr_satp, - `csr_medeleg, - `csr_mideleg, - `csr_dcsr, - `csr_dpc, - `csr_dscratch: - get_csr_op_is_valid = 0; - `csr_cycle, - `csr_time, - `csr_instret, - `csr_cycleh, - `csr_timeh, - `csr_instreth, - `csr_mvendorid, - `csr_marchid, - `csr_mimpid, - `csr_mhartid: - get_csr_op_is_valid = ~csr_writes; - `csr_misa, - `csr_mstatus, - `csr_mie, - `csr_mtvec, - `csr_mscratch, - `csr_mepc, - `csr_mcause, - `csr_mip: - get_csr_op_is_valid = 1; - `csr_mcounteren, - `csr_mtval, - `csr_mcycle, - `csr_minstret, - `csr_mcycleh, - `csr_minstreth: - // TODO: CSRs not implemented yet - get_csr_op_is_valid = 0; - endcase - end - endfunction - - assign csr_op_is_valid = get_csr_op_is_valid(csr_number, csr_reads, csr_writes); - - wire [63:0] cycle_counter = 0; // TODO: implement cycle_counter - wire [63:0] time_counter = 0; // TODO: implement time_counter - wire [63:0] instret_counter = 0; // TODO: implement instret_counter - always @(posedge clk) begin:main_block if(reset) begin reset_to_initial();