X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=cpu.py;h=9d50e5936e57137fd44f7719b4874b7738853ed7;hb=b0d897238492346241e62d168ac7ca57ea3e14b1;hp=d654989e717a164d5b16368f975193ad9547be39;hpb=3cea524b956ff52f3118b83f2b71031cd86730b9;p=rv32.git diff --git a/cpu.py b/cpu.py index d654989..9d50e59 100644 --- a/cpu.py +++ b/cpu.py @@ -241,6 +241,82 @@ class Fetch: return Case(self.output_state, c) +class CSR: + def __init__(self, comb, sync, dc, register_rs1): + self.comb = comb + self.sync = sync + self.number = Signal(12, name="csr_number") + self.input_value = Signal(32, name="csr_input_value") + self.reads = Signal(name="csr_reads") + self.writes = Signal(name="csr_writes") + self.op_is_valid = Signal(name="csr_op_is_valid") + + self.comb += self.number.eq(dc.immediate) + self.comb += self.input_value.eq(Mux(dc.funct3[2], + dc.rs1, + register_rs1)) + self.comb += self.reads.eq(dc.funct3[1] | (dc.rd != 0)) + self.comb += self.writes.eq(~dc.funct3[1] | (dc.rs1 != 0)) + + self.comb += self.get_csr_op_is_valid() + + def get_csr_op_is_valid(self): + """ determines if a CSR is valid + """ + c = {} + # invalid csrs + for f in [csr_ustatus, csr_fflags, csr_frm, csr_fcsr, + csr_uie, csr_utvec, csr_uscratch, csr_uepc, + csr_ucause, csr_utval, csr_uip, csr_sstatus, + csr_sedeleg, csr_sideleg, csr_sie, csr_stvec, + csr_scounteren, csr_sscratch, csr_sepc, csr_scause, + csr_stval, csr_sip, csr_satp, csr_medeleg, + csr_mideleg, csr_dcsr, csr_dpc, csr_dscratch]: + c[f] = self.op_is_valid.eq(0) + + # not-writeable -> ok + for f in [csr_cycle, csr_time, csr_instret, csr_cycleh, + csr_timeh, csr_instreth, csr_mvendorid, csr_marchid, + csr_mimpid, csr_mhartid]: + c[f] = self.op_is_valid.eq(~self.writes) + + # valid csrs + for f in [csr_misa, csr_mstatus, csr_mie, csr_mtvec, + csr_mscratch, csr_mepc, csr_mcause, csr_mip]: + c[f] = self.op_is_valid.eq(1) + + # not implemented / default + for f in [csr_mcounteren, csr_mtval, csr_mcycle, csr_minstret, + csr_mcycleh, csr_minstreth, "default"]: + c[f] = self.op_is_valid.eq(0) + + return Case(self.number, c) + + def evaluate_csr_funct3_op(self, funct3, previous_value, written_value): + c = { "default": Constant(0, 32)} + for f in [F3.csrrw, F3.csrrwi]: c[f] = written_value + for f in [F3.csrrs, F3.csrrsi]: c[f] = written_value | previous_value + for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value + return Case(funct3, c) + + +class MInfo: + def __init__(self, comb): + self.comb = comb + # TODO + self.cycle_counter = Signal(64); # TODO: implement cycle_counter + self.time_counter = Signal(64); # TODO: implement time_counter + self.instret_counter = Signal(64); # TODO: implement instret_counter + + self.mvendorid = Signal(32) + self.marchid = Signal(32) + self.mimpid = Signal(32) + self.mhartid = Signal(32) + self.comb += self.mvendorid.eq(Constant(0, 32)) + self.comb += self.marchid.eq(Constant(0, 32)) + self.comb += self.mimpid.eq(Constant(0, 32)) + self.comb += self.mhartid.eq(Constant(0, 32)) + class CPU(Module): """ @@ -273,13 +349,6 @@ class CPU(Module): self.registers[register_number].eq(value) ) - def evaluate_csr_funct3_op(self, funct3, previous_value, written_value): - c = { "default": Constant(0, 32)} - for f in [F3.csrrw, F3.csrrwi]: c[f] = written_value - for f in [F3.csrrs, F3.csrrsi]: c[f] = written_value | previous_value - for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value - return Case(funct3, c) - def handle_trap(self, m, ms, ft, dc, load_store_misaligned): s = [ms.mpie.eq(ms.mie), ms.mie.eq(0), @@ -328,57 +397,25 @@ class CPU(Module): s.append(i) return s - def get_csr_op_is_valid(self, csr_op_is_valid, csr_number, - csr_reads, csr_writes): - """ determines if a CSR is valid - """ - c = {} - # invalid csrs - for f in [csr_ustatus, csr_fflags, csr_frm, csr_fcsr, - csr_uie, csr_utvec, csr_uscratch, csr_uepc, - csr_ucause, csr_utval, csr_uip, csr_sstatus, - csr_sedeleg, csr_sideleg, csr_sie, csr_stvec, - csr_scounteren, csr_sscratch, csr_sepc, csr_scause, - csr_stval, csr_sip, csr_satp, csr_medeleg, - csr_mideleg, csr_dcsr, csr_dpc, csr_dscratch]: - c[f] = csr_op_is_valid.eq(0) - - # not-writeable -> ok - for f in [csr_cycle, csr_time, csr_instret, csr_cycleh, - csr_timeh, csr_instreth, csr_mvendorid, csr_marchid, - csr_mimpid, csr_mhartid]: - c[f] = csr_op_is_valid.eq(~csr_writes) - - # valid csrs - for f in [csr_misa, csr_mstatus, csr_mie, csr_mtvec, - csr_mscratch, csr_mepc, csr_mcause, csr_mip]: - c[f] = csr_op_is_valid.eq(1) - - # not implemented / default - for f in [csr_mcounteren, csr_mtval, csr_mcycle, csr_minstret, - csr_mcycleh, csr_minstreth, "default"]: - c[f] = csr_op_is_valid.eq(0) - - return Case(csr_number, c) - - def main_block(self, mi, m, mstatus, ft, dc, load_store_misaligned, + def main_block(self, minfo, csr, mi, m, mstatus, ft, dc, + load_store_misaligned, loaded_value, alu_result, - lui_auipc_result, fetch_output_pc): + lui_auipc_result): c = {} c[FOS.empty] = [] c[FOS.trap] = self.handle_trap(m, mstatus, ft, dc, load_store_misaligned) - c[FOS.valid] = self.handle_valid(mi, m, mstatus, ft, dc, + c[FOS.valid] = self.handle_valid(minfo, csr, mi, m, mstatus, ft, dc, load_store_misaligned, loaded_value, alu_result, - lui_auipc_result, - fetch_output_pc) + lui_auipc_result) return Case(ft.output_state, c) - def handle_valid(self, mi, m, mstatus, ft, dc, load_store_misaligned, + def handle_valid(self, minfo, csr, mi, m, mstatus, ft, dc, + load_store_misaligned, loaded_value, alu_result, - lui_auipc_result, fetch_output_pc): + lui_auipc_result): # fetch action ack trap i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap), self.handle_trap(m, mstatus, ft, dc, @@ -404,7 +441,11 @@ class CPU(Module): # jal/jalr i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0, - self.write_register(dc.rd, fetch_output_pc + 4) + self.write_register(dc.rd, ft.output_pc + 4) + ) + + i = i.Elif((dc.act & DA.csr) != 0, + self.handle_csr(minfo, mstatus, dc, csr) ) # fence, store, branch @@ -415,8 +456,14 @@ class CPU(Module): return i + def handle_csr(self, minfo, mstatus, dc, csr): + csr_output_value = Signal() + csr_written_value = Signal() + c = {} + + return Case(csr.number, c) + """ - else if((decode_action & `decode_action_csr) != 0) begin:csr reg [31:0] csr_output_value; reg [31:0] csr_written_value; csr_output_value = 32'hXXXXXXXX; @@ -761,55 +808,24 @@ class CPU(Module): m = M(self.comb, self.sync) mstatus = MStatus(self.comb, self.sync) mie = MIE(self.comb, self.sync) - misa = Misa(self.comb, self.sync) - - mvendorid = Signal(32) - marchid = Signal(32) - mimpid = Signal(32) - mhartid = Signal(32) - self.comb += mvendorid.eq(Constant(0, 32)) - self.comb += marchid.eq(Constant(0, 32)) - self.comb += mimpid.eq(Constant(0, 32)) - self.comb += mhartid.eq(Constant(0, 32)) - mip = MIP(self.comb, self.sync) - csr_op_is_valid = Signal() + # CSR decoding + csr = CSR(self.comb, self.sync, dc, register_rs1) self.comb += ft.get_fetch_action(dc, load_store_misaligned, mi, branch_taken, misaligned_jump_target, - csr_op_is_valid) - - #self.comb += self.handle_trap(m, mstatus, ft, dc, load_store_misaligned) - # CSR decoding - csr_number = Signal(12) - csr_input_value = Signal(32) - csr_reads = Signal() - csr_writes = Signal() + csr.op_is_valid) - self.comb += csr_number.eq(dc.immediate) - self.comb += csr_input_value.eq(Mux(dc.funct3[2], - dc.rs1, - register_rs1)) - self.comb += csr_reads.eq(dc.funct3[1] | (dc.rd != 0)) - self.comb += csr_writes.eq(~dc.funct3[1] | (dc.rs1 != 0)) - - self.comb += self.get_csr_op_is_valid(csr_op_is_valid, csr_number, - csr_reads, csr_writes) - - # TODO - cycle_counter = Signal(64); # TODO: implement cycle_counter - time_counter = Signal(64); # TODO: implement time_counter - instret_counter = Signal(64); # TODO: implement instret_counter + minfo = MInfo(self.comb) self.sync += If(~self.reset, - self.main_block(mi, m, mstatus, ft, dc, + self.main_block(minfo, csr, mi, m, mstatus, ft, dc, load_store_misaligned, loaded_value, alu_result, - lui_auipc_result, - fetch_output_pc) + lui_auipc_result) ) if __name__ == "__main__":