X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=cpu_fetch_stage.py;h=1fa8942f08bb61e275b59e98a3ce19f8f5dfc45c;hb=3bd2acbd6ad7a2cae991ac9726d665e03dd84e05;hp=f35e68c447c491032cc05b2ae0804450c0d4322a;hpb=6bba190794140001bb515d2b4085b31a89731a41;p=rv32.git

diff --git a/cpu_fetch_stage.py b/cpu_fetch_stage.py
index f35e68c..1fa8942 100644
--- a/cpu_fetch_stage.py
+++ b/cpu_fetch_stage.py
@@ -26,11 +26,11 @@
 from migen import *
 from migen.fhdl import verilog
 
-from riscvdefs import *
+#from riscvdefs import *
 from cpudefs import *
 
-reset_vector = 32'hXXXXXXXX;
-mtvec = 32'hXXXXXXXX;
+reset_vector = 0x0 #32'hXXXXXXXX;
+mtvec = 0x0 # 32'hXXXXXXXX;
 
 class CPUFetchStage(Module):
     def __init__(self):
@@ -41,58 +41,85 @@ class CPUFetchStage(Module):
         #input [31:0] memory_interface_fetch_data,
         self.memory_interface_fetch_data = Signal(32)
         self.memory_interface_fetch_valid = Signal()
-        input `fetch_action fetch_action,
-        input [31:0] target_pc,
+        self.fetch_action = Signal(fetch_action)
+        self.target_pc = Signal(32)
         self.output_pc = Signal(32, reset=reset_vector)
         self.output_instruction = Signal(32)
-        output reg `fetch_output_state output_state
+        self.output_state = Signal(fetch_output_state,
+                                   reset=fetch_output_state_empty)
 
-        self.comb += [
-            self.cd_sys.clk.eq(self.clk),
-            self.cd_sys.rst.eq(self.reset)
-        ]
+        #self.comb += [
+        #    self.cd_sys.clk.eq(self.clk),
+        #    self.cd_sys.rst.eq(self.reset)
+        #]
 
         fetch_pc = Signal(32, reset=reset_vector)
 
-        self.sync += output_pc.eq((fetch_action == `fetch_action_wait) ? output_pc : fetch_pc);
+        self.sync += If(self.fetch_action != fetch_action_wait,
+                        self.output_pc.eq(fetch_pc))
 
-        memory_interface_fetch_address = fetch_pc[2:]
+        self.memory_interface_fetch_address = fetch_pc[2:]
 
-        initial output_pc <= reset_vector;
-        initial output_state <= `fetch_output_state_empty;
+        #initial output_pc <= reset_vector;
+        #initial output_state <= `fetch_output_state_empty;
 
-        delayed_instruction = Signal(32, reset=0);
-        delayed_instruction_valid = Signal(reset=0);
+        delayed_instruction = Signal(32, reset=0)
+        delayed_instruction_valid = Signal(reset=0)
 
-        self.sync += delayed_instruction.eq(output_instruction)
-        self.sync += output_state.eq(fetch_output_state_empty)
+        self.sync += delayed_instruction.eq(self.output_instruction)
+        self.sync += self.output_state.eq(fetch_output_state_empty)
 
-        self.comb += output_instruction.eq(delayed_instruction_valid ? delayed_instruction : memory_interface_fetch_data)
+        self.comb += If(delayed_instruction_valid,
+                    self.output_instruction.eq(delayed_instruction)
+                ).Else(
+                    self.output_instruction.eq(self.memory_interface_fetch_data)
+                )
 
-        self.sync += delayed_instruction_valid.eq(fetch_action == `fetch_action_wait)
+        self.sync += delayed_instruction_valid.eq(self.fetch_action ==
+                                                  fetch_action_wait)
 
-        fc = {}
-        self.comb += Case(fetch_action, fc)
-        fc[fetch_action_ack_trap] =
-                If(memory_interface_fetch_valid,
+        fc = {
+            fetch_action_ack_trap:
+                If(self.memory_interface_fetch_valid,
                    [fetch_pc.eq(fetch_pc + 4),
-                    output_state.eq(fetch_output_state_valid)]
+                    self.output_state.eq(fetch_output_state_valid)]
                 ).Else(
                    [fetch_pc.eq(mtvec),
-                    output_state.eq(fetch_output_state_trap)]
-                )
-        fc[fetch_action_default] = fc[fetch_action_ack_trap]
-        fc[fetch_action_fence] =
-                [ fetch_pc.eq(output_pc + 4),
-                  output_state.eq(fetch_output_state_empty)]
-        fc[fetch_action_jump] =
-                [ fetch_pc.eq(target_pc),
-                  output_state.eq(fetch_output_state_empty)]
-        fc[fetch_action_error_trap] =
+                    self.output_state.eq(fetch_output_state_trap)]
+                ),
+            fetch_action_fence:
+                [ fetch_pc.eq(self.output_pc + 4),
+                  self.output_state.eq(fetch_output_state_empty)
+                ],
+            fetch_action_jump:
+                [ fetch_pc.eq(self.target_pc),
+                  self.output_state.eq(fetch_output_state_empty)
+                ],
+            fetch_action_error_trap:
                    [fetch_pc.eq(mtvec),
-                    output_state.eq(fetch_output_state_empty)]
-        fc[fetch_action_noerror_trap] = fc[fetch_action_error_trap]
-        fc[fetch_action_wait] =
+                    self.output_state.eq(fetch_output_state_empty)
+                ],
+            fetch_action_wait:
                    [fetch_pc.eq(fetch_pc),
-                    output_state.eq(fetch_output_state_valid)]
+                    self.output_state.eq(fetch_output_state_valid)
+                ]
+        }
+        fc[fetch_action_default] = fc[fetch_action_ack_trap]
+        fc[fetch_action_noerror_trap] = fc[fetch_action_error_trap]
+        self.sync += Case(self.fetch_action,
+                          fc).makedefault(fetch_action_default)
 
+if __name__ == "__main__":
+    example = CPUFetchStage()
+    memory_interface_fetch_address = Signal(32)
+    print(verilog.convert(example,
+         { #example.clk,
+           #example.reset,
+           memory_interface_fetch_address,
+           example.memory_interface_fetch_data,
+           example.memory_interface_fetch_valid,
+           example.fetch_action,
+           example.target_pc,
+           example.output_pc,
+           example.output_instruction,
+           example.output_state }))