X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=cpu_fetch_stage.py;h=3d25d3507cdf8362b5467bbca2cf51240559affe;hb=84762ebcde7d4dc6493571f7337637e747139876;hp=f35e68c447c491032cc05b2ae0804450c0d4322a;hpb=6bba190794140001bb515d2b4085b31a89731a41;p=rv32.git

diff --git a/cpu_fetch_stage.py b/cpu_fetch_stage.py
index f35e68c..3d25d35 100644
--- a/cpu_fetch_stage.py
+++ b/cpu_fetch_stage.py
@@ -41,11 +41,12 @@ class CPUFetchStage(Module):
         #input [31:0] memory_interface_fetch_data,
         self.memory_interface_fetch_data = Signal(32)
         self.memory_interface_fetch_valid = Signal()
-        input `fetch_action fetch_action,
-        input [31:0] target_pc,
+        self.fetch_action = Signal(fetch_action)
+        self.target_pc = Signal(32)
         self.output_pc = Signal(32, reset=reset_vector)
         self.output_instruction = Signal(32)
-        output reg `fetch_output_state output_state
+        self.output_state = Signal(fetch_output_state,
+                                   reset=fetch_output_state_empty)
 
         self.comb += [
             self.cd_sys.clk.eq(self.clk),
@@ -54,7 +55,11 @@ class CPUFetchStage(Module):
 
         fetch_pc = Signal(32, reset=reset_vector)
 
-        self.sync += output_pc.eq((fetch_action == `fetch_action_wait) ? output_pc : fetch_pc);
+        self.sync += If(fetch_action != fetch_action_wait,
+                        output_pc.eq(fetch_pc)).
+                     Else( output_pc.eq(output_pc)) # hmmm...
+        #self.sync += output_pc.eq((fetch_action == `fetch_action_wait) ?
+        #                          output_pc : fetch_pc);
 
         memory_interface_fetch_address = fetch_pc[2:]
 
@@ -67,32 +72,42 @@ class CPUFetchStage(Module):
         self.sync += delayed_instruction.eq(output_instruction)
         self.sync += output_state.eq(fetch_output_state_empty)
 
-        self.comb += output_instruction.eq(delayed_instruction_valid ? delayed_instruction : memory_interface_fetch_data)
+        self.comb += If(delayed_instruction_valid,
+                    output_instruction.eq(delayed_instruction)
+                ).Else(
+                    output_instruction.eq(memory_interface_fetch_data)
+                )
 
-        self.sync += delayed_instruction_valid.eq(fetch_action == `fetch_action_wait)
+        self.sync += delayed_instruction_valid.eq(fetch_action ==
+                                                  fetch_action_wait)
 
-        fc = {}
-        self.comb += Case(fetch_action, fc)
-        fc[fetch_action_ack_trap] =
+        fc = {
+            fetch_action_ack_trap:
                 If(memory_interface_fetch_valid,
                    [fetch_pc.eq(fetch_pc + 4),
                     output_state.eq(fetch_output_state_valid)]
                 ).Else(
                    [fetch_pc.eq(mtvec),
                     output_state.eq(fetch_output_state_trap)]
-                )
-        fc[fetch_action_default] = fc[fetch_action_ack_trap]
-        fc[fetch_action_fence] =
+                ),
+            fetch_action_fence:
                 [ fetch_pc.eq(output_pc + 4),
-                  output_state.eq(fetch_output_state_empty)]
-        fc[fetch_action_jump] =
+                  output_state.eq(fetch_output_state_empty)
+                ],
+            fetch_action_jump:
                 [ fetch_pc.eq(target_pc),
-                  output_state.eq(fetch_output_state_empty)]
-        fc[fetch_action_error_trap] =
+                  output_state.eq(fetch_output_state_empty)
+                ],
+            fetch_action_error_trap,
                    [fetch_pc.eq(mtvec),
-                    output_state.eq(fetch_output_state_empty)]
-        fc[fetch_action_noerror_trap] = fc[fetch_action_error_trap]
-        fc[fetch_action_wait] =
+                    output_state.eq(fetch_output_state_empty)
+                ],
+            fetch_action_wait:
                    [fetch_pc.eq(fetch_pc),
-                    output_state.eq(fetch_output_state_valid)]
+                    output_state.eq(fetch_output_state_valid)
+                ]
+        }
+        fc[fetch_action_default] = fc[fetch_action_ack_trap]
+        fc[fetch_action_noerror_trap] = fc[fetch_action_error_trap]
+        self.sync += Case(fetch_action, fc).makedefault(fetch_action_default)