X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=cpu_fetch_stage.py;h=820591efa2ab76c723b357712ab51f14aa192c69;hb=d364e8c2247fd1914b63f51e19fce1584f91ad39;hp=7c699bd13cb9645d61523c7b1bfd346b3dadeca0;hpb=c803923c6e7d929197bc5bb4643aa98c1ab6835a;p=rv32.git

diff --git a/cpu_fetch_stage.py b/cpu_fetch_stage.py
index 7c699bd..820591e 100644
--- a/cpu_fetch_stage.py
+++ b/cpu_fetch_stage.py
@@ -67,7 +67,6 @@ class CPUFetchStage(Module):
         delayed_instruction_valid = Signal(reset=0)
 
         self.sync += delayed_instruction.eq(self.output_instruction)
-        self.sync += self.output_state.eq(fetch_output_state_empty)
 
         self.comb += If(delayed_instruction_valid,
                     self.output_instruction.eq(delayed_instruction)