X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=debug%2Fprograms%2Fentry.S;h=3acd786cc226d367ddc109cb03a53e11f2601b45;hb=a96f32d19d65123a5cf4e43aa25e503530f910b9;hp=80904cdb38191967deb1958e18955c4365fc1c91;hpb=a27ddca0570517e7e40a91c16e4c96c6c5f329e1;p=riscv-tests.git diff --git a/debug/programs/entry.S b/debug/programs/entry.S index 80904cd..3acd786 100755 --- a/debug/programs/entry.S +++ b/debug/programs/entry.S @@ -1,11 +1,8 @@ -#ifndef ENTRY_S -#define ENTRY_S - #include "encoding.h" -#define STACK_SIZE 512 +#define STACK_SIZE (90 * XLEN / 8) -#ifdef __riscv64 +#if XLEN == 64 # define LREG ld # define SREG sd # define REGBYTES 8 @@ -27,23 +24,89 @@ trap_vector: j trap_entry handle_reset: - la t0, trap_entry + // If misa doesn't exist (or is following an old spec where it has a + // different number), skip the next block. + la t0, 3f csrw mtvec, t0 csrwi mstatus, 0 + + // make sure these registers exist by seeing if either S or U bits + // are set before attempting to zero them out. + csrr t1, misa + addi t2, x0, 1 + slli t2, t2, 20 // U_EXTENSION + and t2, t1, t2 + bne x0, t2, 1f + addi t2, x0, 1 + slli t2, t2, 18 // S_EXTENSION + and t2, t1, t2 + bne x0, t2, 1f + j 2f +1: csrwi mideleg, 0 csrwi medeleg, 0 +2: csrwi mie, 0 +3: + la t0, trap_entry + csrw mtvec, t0 + csrwi mstatus, 0 # initialize global pointer - la gp, _gp +.option push +.option norelax + la gp, __global_pointer$ +.option pop + + # Initialize stack pointer. + # Give each hart STACK_SIZE of stack. + # Assume hart IDs are contiguous and start at 0. + csrr t0, CSR_MHARTID + addi t0, t0, 1 + li t1, STACK_SIZE + mul t0, t0, t1 + la sp, stack_bottom + add sp, sp, t0 + + # Clear all hardware triggers + li t0, ~0 +1: + addi t0, t0, 1 + csrw CSR_TSELECT, t0 + csrw CSR_TDATA1, zero + csrr t1, CSR_TSELECT + beq t0, t1, 1b + +#ifdef MULTICORE + csrr t0, CSR_MHARTID + bnez t0, wait_until_initialized +#endif - # initialize stack pointer - la sp, stack_top + la t0, __bss_start + la t1, __bss_end +1: + bge t0, t1, 2f + sb zero, 0(t0) + addi t0, t0, 1 + j 1b +2: +#ifdef MULTICORE + la t0, initialized + li t1, 1 + sw t1, 0(t0) + +wait_until_initialized: # Wait for hart 0 to perform initialization. + la t0, initialized +1: + lw t1, 0(t0) + beqz t1, 1b +#endif # perform the rest of initialization in C - j _init + j _init +.align 2 trap_entry: addi sp, sp, -32*REGBYTES @@ -124,9 +187,14 @@ trap_entry: addi sp, sp, 32*REGBYTES mret +loop_forever: + j loop_forever + // Fill the stack with data so we can see if it was overrun. + .section .data .align 4 stack_bottom: - .fill STACK_SIZE/4, 4, 0x22446688 + .fill NHARTS * STACK_SIZE/4, 4, 0x22446688 stack_top: -#endif +initialized: + .word 0