X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=debug%2Fprograms%2Ftrigger.S;h=13f044978c830ecf31e72dfecc14503ccf4ef7db;hb=ba39c5fc2885eb1400d6f9e13ae6c7588c1c1241;hp=48cd68b024ee46df6ed2b13343a6cfa648ab2a88;hpb=56f46aa0f9688c87ce9ebd7658e19b884b018b6b;p=riscv-tests.git

diff --git a/debug/programs/trigger.S b/debug/programs/trigger.S
index 48cd68b..13f0449 100644
--- a/debug/programs/trigger.S
+++ b/debug/programs/trigger.S
@@ -1,6 +1,6 @@
-#include "../../env/encoding.h"
+#include "encoding.h"
 
-#if __riscv_xlen == 64
+#if XLEN == 64
 # define LREG ld
 # define SREG sd
 # define REGBYTES 8
@@ -8,16 +8,6 @@
 # define LREG lw
 # define SREG sw
 # define REGBYTES 4
-#endif
-
-#undef MCONTROL_TYPE
-#undef MCONTROL_DMODE
-#if __riscv_xlen == 64
-# define MCONTROL_TYPE    (0xf<<(64-4))
-# define MCONTROL_DMODE   (1<<(64-5))
-#else
-# define MCONTROL_TYPE    (0xf<<(32-4))
-# define MCONTROL_DMODE   (1<<(32-5))
 #endif
 
         .global         main
@@ -31,7 +21,10 @@ just_before_read_loop:
         li      t2, 16
 read_loop:
         lw      t1, 0(a0)
+        addi    t1, t1, 1
         addi    t0, t0, 1
+read_again:
+        lw      t1, 0(a0)
         addi    a0, a0, 4
         blt     t0, t2, read_loop
 
@@ -101,6 +94,7 @@ read_triggers:
         ret
 
         .data
+        .align  3
 data:   .word   0x40
         .word   0x41
         .word   0x42