X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=debug%2Ftargets%2FRISC-V%2Fspike32-2.py;h=6c90b7c87f808d9b2a229072417365e3a67357b1;hb=4dddbc79ada7f0a836cf538676c57c8df103ccf6;hp=a7b9a1c0a7a1b244afef8f4980554cbd8ec6b53c;hpb=35c41f1391b51d4d9c4e0ab40fdfc45dbea346b2;p=riscv-tests.git

diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py
index a7b9a1c..6c90b7c 100644
--- a/debug/targets/RISC-V/spike32-2.py
+++ b/debug/targets/RISC-V/spike32-2.py
@@ -5,8 +5,9 @@ import spike32  # pylint: disable=import-error
 
 class spike32_2(targets.Target):
     harts = [spike32.spike32_hart(), spike32.spike32_hart()]
-    openocd_config_path = "spike-rtos.cfg"
+    openocd_config_path = "spike-2.cfg"
     timeout_sec = 30
+    implements_custom_test = True
 
     def create(self):
-        return testlib.Spike(self)
+        return testlib.Spike(self, isa="RV32IMAFC", progbufsize=0)