X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=debug%2Ftargets%2FSiFive%2FHiFive1.py;h=3cb508cd0e1e358797ce7f836ffc6fdcc5046ad7;hb=3a44725d27f6b2c77f0ca912d792b6856fde6a17;hp=813829e415116ec15a76c463924f168c14f83c87;hpb=ab6c2ccaec192684cf4649d5d69bd105d738d1c7;p=riscv-tests.git

diff --git a/debug/targets/SiFive/HiFive1.py b/debug/targets/SiFive/HiFive1.py
index 813829e..3cb508c 100644
--- a/debug/targets/SiFive/HiFive1.py
+++ b/debug/targets/SiFive/HiFive1.py
@@ -1,8 +1,11 @@
 import targets
 
-class HiFive1(targets.Target):
+class HiFive1Hart(targets.Hart):
     xlen = 32
     ram = 0x80000000
     ram_size = 16 * 1024
     instruction_hardware_breakpoint_count = 2
     misa = 0x40001105
+
+class HiFive1(targets.Target):
+    harts = [HiFive1Hart()]