X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=debug%2Ftestlib.py;h=3aaa542a5c76dce60bf92ca485119e2045b3dbe0;hb=ba39c5fc2885eb1400d6f9e13ae6c7588c1c1241;hp=b19eafcb865f6bfa97f51674930137843541e86c;hpb=4590b79bc7241f3fa2424f96b4c6666a864fb6a9;p=riscv-tests.git diff --git a/debug/testlib.py b/debug/testlib.py index b19eafc..3aaa542 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -9,6 +9,7 @@ import sys import tempfile import time import traceback +import pipes import pexpect @@ -55,10 +56,12 @@ def compile(args, xlen=32): # pylint: disable=redefined-builtin raise Exception("Compile failed!") class Spike(object): - def __init__(self, target, halted=False, timeout=None, with_jtag_gdb=True): + def __init__(self, target, halted=False, timeout=None, with_jtag_gdb=True, + isa=None): """Launch spike. Return tuple of its process and the port it's running on.""" self.process = None + self.isa = isa if target.harts: harts = target.harts @@ -108,10 +111,12 @@ class Spike(object): assert len(set(t.xlen for t in harts)) == 1, \ "All spike harts must have the same XLEN" - if harts[0].xlen == 32: - cmd += ["--isa", "RV32G"] + if self.isa: + isa = self.isa else: - cmd += ["--isa", "RV64G"] + isa = "RV%dG" % harts[0].xlen + + cmd += ["--isa", isa] assert len(set(t.ram for t in harts)) == 1, \ "All spike harts must have the same RAM layout" @@ -142,9 +147,10 @@ class Spike(object): return self.process.wait(*args, **kwargs) class VcsSim(object): - logname = "simv.log" + logfile = tempfile.NamedTemporaryFile(prefix='simv', suffix='.log') + logname = logfile.name - def __init__(self, sim_cmd=None, debug=False): + def __init__(self, sim_cmd=None, debug=False, timeout=300): if sim_cmd: cmd = shlex.split(sim_cmd) else: @@ -153,14 +159,19 @@ class VcsSim(object): if debug: cmd[0] = cmd[0] + "-debug" cmd += ["+vcdplusfile=output/gdbserver.vpd"] + logfile = open(self.logname, "w") + if print_log_names: + real_stdout.write("Temporary VCS log: %s\n" % self.logname) logfile.write("+ %s\n" % " ".join(cmd)) logfile.flush() + listenfile = open(self.logname, "r") listenfile.seek(0, 2) self.process = subprocess.Popen(cmd, stdin=subprocess.PIPE, stdout=logfile, stderr=logfile) done = False + start = time.time() while not done: # Fail if VCS exits early exit_code = self.process.poll() @@ -177,6 +188,10 @@ class VcsSim(object): self.port = int(match.group(1)) os.environ['JTAG_VPI_PORT'] = str(self.port) + if (time.time() - start) > timeout: + raise Exception("Timed out waiting for VCS to listen for JTAG " + "vpi") + def __del__(self): try: self.process.kill() @@ -227,7 +242,11 @@ class Openocd(object): logfile = open(Openocd.logname, "w") if print_log_names: real_stdout.write("Temporary OpenOCD log: %s\n" % Openocd.logname) - logfile.write("+ %s\n" % " ".join(cmd)) + env_entries = ("REMOTE_BITBANG_HOST", "REMOTE_BITBANG_PORT") + env_entries = [key for key in env_entries if key in os.environ] + logfile.write("+ %s%s\n" % ( + "".join("%s=%s " % (key, os.environ[key]) for key in env_entries), + " ".join(map(pipes.quote, cmd)))) logfile.flush() self.gdb_ports = [] @@ -310,6 +329,12 @@ class CannotAccess(Exception): Exception.__init__(self) self.address = address +class CouldNotFetch(Exception): + def __init__(self, regname, explanation): + Exception.__init__(self) + self.regname = regname + self.explanation = explanation + Thread = collections.namedtuple('Thread', ('id', 'description', 'target_id', 'name', 'frame')) @@ -371,12 +396,18 @@ class Gdb(object): hartid = max(self.harts) + 1 else: hartid = 0 - self.harts[hartid] = (child, t) + # solo: True iff this is the only thread on this child + self.harts[hartid] = {'child': child, + 'thread': t, + 'solo': len(threads) == 1} def __del__(self): for child in self.children: del child + def one_hart_per_gdb(self): + return all(h['solo'] for h in self.harts.itervalues()) + def lognames(self): return [logfile.name for logfile in self.logfiles] @@ -384,10 +415,11 @@ class Gdb(object): self.active_child = child def select_hart(self, hart): - child, thread = self.harts[hart.id] - self.select_child(child) - output = self.command("thread %s" % thread.id) - assert "Unknown" not in output + h = self.harts[hart.id] + self.select_child(h['child']) + if not h['solo']: + output = self.command("thread %s" % h['thread'].id, timeout=10) + assert "Unknown" not in output def push_state(self): self.stack.append({ @@ -488,6 +520,9 @@ class Gdb(object): m = re.search("Cannot access memory at address (0x[0-9a-f]+)", output) if m: raise CannotAccess(int(m.group(1), 0)) + m = re.search(r"Could not fetch register \"(\w+)\"; (.*)$", output) + if m: + raise CouldNotFetch(m.group(1), m.group(2)) rhs = output.split('=')[-1] return self.parse_string(rhs) @@ -606,6 +641,7 @@ def run_tests(parsed, target, todo): finally: sys.stdout = real_stdout log_fd.write("Time elapsed: %.2fs\n" % (time.time() - start)) + log_fd.flush() print "[%s] %s in %.2fs" % (name, result, time.time() - start) if result not in good_results and parsed.print_failures: sys.stdout.write(open(log_name).read()) @@ -784,7 +820,6 @@ class GdbTest(BaseTest): self.logs += self.gdb.lognames() self.gdb.connect() - self.gdb.global_command("set arch riscv:rv%d" % self.hart.xlen) self.gdb.global_command("set remotetimeout %d" % self.target.timeout_sec) @@ -800,6 +835,7 @@ class GdbTest(BaseTest): if not self.gdb: return self.gdb.interrupt() + self.gdb.command("disassemble") self.gdb.command("info registers all", timeout=10) def classTeardown(self): @@ -836,8 +872,9 @@ class ExamineTarget(GdbTest): raise TestFailed("Couldn't determine XLEN from $misa (0x%x)" % self.hart.misa) - if (misa_xlen != hart.xlen): - raise TestFailed("MISA reported XLEN of %d but we were expecting XLEN of %d\n" % (misa_xlen, hart.xlen)) + if misa_xlen != hart.xlen: + raise TestFailed("MISA reported XLEN of %d but we were "\ + "expecting XLEN of %d\n" % (misa_xlen, hart.xlen)) txt += ("%d" % misa_xlen)