X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=harmonised_rvv_rvp%2Fcomparative_analysis.mdwn;h=9b694a2f1bd4e59ae559abf18356e02bedd5f0eb;hb=87a4dce6f5349b17dbf02b90aeecb61ae4688ac3;hp=a33b5f3c1be746e974c7e40503b7ce28c0c5d270;hpb=1bb84acf1fe105d7e72268de2449f04b19223966;p=libreriscv.git diff --git a/harmonised_rvv_rvp/comparative_analysis.mdwn b/harmonised_rvv_rvp/comparative_analysis.mdwn index a33b5f3c1..9b694a2f1 100644 --- a/harmonised_rvv_rvp/comparative_analysis.mdwn +++ b/harmonised_rvv_rvp/comparative_analysis.mdwn @@ -56,7 +56,7 @@ To keep implementations simple and focused on SIMD within­-register only, there Harmonised RVP re-uses the same RV Vector opcodes to encode RVP SIMD instructions on *integer* registers. This is a deliberate design, to provide a means for binary code to be forwards compatible between RVP and RV Vector. -Such "forwards compatible" code will need to take care to respect normal calling conventions (ie: save callee saved GPR registers before loading vectors into register - this is harmless but redundant behaviour on RV Vector implementations dedicated vector registers). +Such "forwards compatible" code will need to take care to respect normal calling conventions (ie: save callee saved GPR registers before loading vectors into register - this is harmless but redundant behaviour on RV Vector implementations with dedicated vector registers). Register x 2 ­--> register operations: