X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=interrupts.mdwn;h=300ed7b1897480333be4dc1426c71e474cb1b6ca;hb=891c074f8cbd5a7742ff9a0dcd5d392b56055dad;hp=f62af414839fb464f6e8f50b8ef94502e6a94d3c;hpb=551e1149aeede0945228fe10963cf896a90c77b8;p=libreriscv.git

diff --git a/interrupts.mdwn b/interrupts.mdwn
index f62af4148..300ed7b18 100644
--- a/interrupts.mdwn
+++ b/interrupts.mdwn
@@ -9,6 +9,10 @@ of interrupt handling is here: [[interrupt_handling]].
 * <https://github.com/RoaLogic/plic> - written in verilog, has an
     AHB3-Lite / AMBA interface.  Documentation is here:
     <https://github.com/RoaLogic/plic/blob/master/DATASHEET.md>
+    It has been taped out, it supports virtually unlimited (limited by
+    timing only) IRQ lines.  All registers are dynamically generated. 
+    Currently it only features an AHB3 slave interface, but the BIU is
+    separate. So other interfaces can be easily added.
 * Shakti Peripherals, there is a tested (taped-out) version here
   in src/peripherals/plic <https://bitbucket.org/casl/c-class/src/>
   and another version with up to 1024 IRQ lines and a 2-cycle