X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=isa%2Fmacros%2Fsimplev%2Fsv_test_macros.h;h=6c671df0e17cf5851238ee442480cba5ba435ba1;hb=c7758747574b99c11d9083b7235887569de61d19;hp=0395755164b8e89e89f71f987c8e93f8e1608e02;hpb=03f51ad496365ebc1fa869d5c080431961080a70;p=riscv-tests.git

diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
index 0395755..6c671df 100644
--- a/isa/macros/simplev/sv_test_macros.h
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -41,6 +41,10 @@
         la      x1, from; \
         fld     reg, offs(x1)
 
+#define SV_FLW_DATA( reg, from, offs ) \
+        la      x1, from; \
+        flw     reg, offs(x1)
+
 #define TEST_SV_IMM( reg, imm ) \
         li      t6, ((imm) & 0xffffffffffffffff); \
         bne     reg, t6, fail
@@ -54,6 +58,15 @@
         fmv.x.d x2, freg; \
         bne     x2, x1, fail
 
+#define TEST_SV_FW( flags, freg, from, offs ) \
+        fsflags x2, x0; \
+        li      x1, flags; \
+        bne     x2, x1, fail; \
+        la      x1, from; \
+        lw      x1, offs(x1); \
+        fmv.x.s x2, freg; \
+        bne     x2, x1, fail
+
 #define SV_W_DFLT 0
 #define SV_W_8BIT 1
 #define SV_W_16BIT 2