X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=isa%2Frv64uc%2Fsv_c_mv.S;h=11a042b920aa4fb18efb2b7763bb55d61924b981;hb=1e383ad459ac835bda65f03881443d78a1fa7444;hp=c85108ce8c548a2ece7836996343760af14ccace;hpb=c5120a0e140003168efd4f6b627783fb82f62965;p=riscv-tests.git

diff --git a/isa/rv64uc/sv_c_mv.S b/isa/rv64uc/sv_c_mv.S
index c85108c..11a042b 100644
--- a/isa/rv64uc/sv_c_mv.S
+++ b/isa/rv64uc/sv_c_mv.S
@@ -23,8 +23,8 @@ RVTEST_CODE_BEGIN   # Start of test code.
         li          x5, 0 # deliberately set x4 to 0
 
         SET_SV_MVL(3)
-        SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1, 0),
-                      SV_REG_CSR(1, 6, 0, 6, 1, 0) )
+        SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1),
+                      SV_REG_CSR(1, 6, 0, 6, 1) )
         SET_SV_VL(3)
 
         .option rvc