X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=isa%2Frv64uc%2Fsv_c_swsp.S;h=7990707e7c1ce2ac5a6f7936c3a4d69fa217ac2a;hb=1e383ad459ac835bda65f03881443d78a1fa7444;hp=c29a9b4a23ae7d67fb839e317adfde8756aa8e03;hpb=c5120a0e140003168efd4f6b627783fb82f62965;p=riscv-tests.git

diff --git a/isa/rv64uc/sv_c_swsp.S b/isa/rv64uc/sv_c_swsp.S
index c29a9b4..7990707 100644
--- a/isa/rv64uc/sv_c_swsp.S
+++ b/isa/rv64uc/sv_c_swsp.S
@@ -22,8 +22,8 @@ RVTEST_CODE_BEGIN
         li          a4, 1004;
 
         SET_SV_MVL(3)
-        SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1, 0),
-                      SV_REG_CSR(1, 2, 0, 2, 1, 0) )
+        SET_SV_2CSRS( SV_REG_CSR(1, 12, 0, 12, 1),
+                      SV_REG_CSR(1, 2, 0, 2, 1) )
         SET_SV_VL(3)
 
   mv a1, sp