X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=isa%2Frv64ud%2Fsv_fadd.S;h=9057dff8e1c2ef531fd871bffb9ef07512a9ee64;hb=1e383ad459ac835bda65f03881443d78a1fa7444;hp=9ef208271f6aff174e91e822209dd09bee9bd993;hpb=c5120a0e140003168efd4f6b627783fb82f62965;p=riscv-tests.git

diff --git a/isa/rv64ud/sv_fadd.S b/isa/rv64ud/sv_fadd.S
index 9ef2082..9057dff 100644
--- a/isa/rv64ud/sv_fadd.S
+++ b/isa/rv64ud/sv_fadd.S
@@ -22,8 +22,8 @@ RVTEST_CODE_BEGIN   # Start of test code.
         SV_FLD_DATA( f8, testdata+56, 0)
 
         SET_SV_MVL(2)
-        SET_SV_2CSRS( SV_REG_CSR(0, 2, 0, 2, 1, 0),
-                      SV_REG_CSR(0, 6, 0, 6, 1, 0) )
+        SET_SV_2CSRS( SV_REG_CSR(0, 2, 0, 2, 1),
+                      SV_REG_CSR(0, 6, 0, 6, 1) )
         SET_SV_VL(2)
 
         fadd.d f2, f2, f6;