X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=isa%2Frv64ui%2Fsv_addi_predicated.S;h=46246ea849eb0ebb92077526fc549dc4eaae4af5;hb=1e383ad459ac835bda65f03881443d78a1fa7444;hp=32902f0e4f6aa1fad925f0f3052a31c66e56cc11;hpb=c5120a0e140003168efd4f6b627783fb82f62965;p=riscv-tests.git

diff --git a/isa/rv64ui/sv_addi_predicated.S b/isa/rv64ui/sv_addi_predicated.S
index 32902f0..46246ea 100644
--- a/isa/rv64ui/sv_addi_predicated.S
+++ b/isa/rv64ui/sv_addi_predicated.S
@@ -13,8 +13,8 @@ RVTEST_RV64U        # Define TVM used by program.
         li      x6, pred;                               \
                                                         \
         SET_SV_MVL( 2);                                  \
-        SET_SV_CSR( 1, 3, 0, 3, 1, 0);                   \
-        SET_SV_PRED_CSR( 1, 3, zero, inv, 6, 1);         \
+        SET_SV_CSR( 1, 3, 0, 3, 1);                    \
+        SET_SV_PRED_CSR( 1, 3, zero, inv, 6, 0);         \
         SET_SV_VL( 2);                                   \
                                                         \
         addi    x3, x3, 1;                              \