X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=isa%2Frv64ui%2Fsv_addi_vector_vector.S;h=8594ba7566f38efe007411888f50862eee5c6d60;hb=1e383ad459ac835bda65f03881443d78a1fa7444;hp=ea1f3c638112b1122d594eb12f601f04898ccf36;hpb=c5120a0e140003168efd4f6b627783fb82f62965;p=riscv-tests.git

diff --git a/isa/rv64ui/sv_addi_vector_vector.S b/isa/rv64ui/sv_addi_vector_vector.S
index ea1f3c6..8594ba7 100644
--- a/isa/rv64ui/sv_addi_vector_vector.S
+++ b/isa/rv64ui/sv_addi_vector_vector.S
@@ -21,8 +21,8 @@ RVTEST_CODE_BEGIN   # Start of test code.
         li          x4, 0 # deliberately set x4 to 0
 
         SET_SV_MVL(2)
-        SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1, 0),
-                      SV_REG_CSR(1, 6, 0, 6, 1, 0) )
+        SET_SV_2CSRS( SV_REG_CSR(1, 3, 0, 3, 1),
+                      SV_REG_CSR(1, 6, 0, 6, 1) )
         SET_SV_VL(2)
 
         addi    x3, x6, 1