X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=openpower%2Fsv%2Frfc%2Fls008.mdwn;h=252270c5d00cec69b0255aa1095a8c1c3ab9e476;hb=924bad992a24ee81a5364fb0b974c003b43a501e;hp=03a9c12907a914367173f8e13ca9dba3d9ee61e7;hpb=d4f8c834818adc2904ee98ff13e4a70ae31e028e;p=libreriscv.git

diff --git a/openpower/sv/rfc/ls008.mdwn b/openpower/sv/rfc/ls008.mdwn
index 03a9c1290..252270c5d 100644
--- a/openpower/sv/rfc/ls008.mdwn
+++ b/openpower/sv/rfc/ls008.mdwn
@@ -98,13 +98,12 @@ Add the following entries to:
 
 # Notation, Section 1.3.2
 
-When register operands (`RA, RT, BF`) are prefixed by a single underscore
-(`_RT, _RA, _BF`) the variable contains the contents of the instruction field
-not the contents of the Register File referenced *by* that field. Example:
-`_RT` contains the contents of bits 5 thru 10. The relationship
-`RT = GPR(_RT)` is thus always true. Uses include making alternative
-decisions within an instruction based on whether the operand field
-is zero or non-zero.
+When destination register operands (`RT, RS`) are prefixed by a single
+underscore (`_RT, _RS`) the variable also contains the contents of the
+instruction field.
+This avoids confusion in pseudocode when a destination register is
+assigned (`RT <- x`) but earlier it was the operand bits that were
+checked (`if RT = 0`)
 
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