X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fdebug_module.cc;h=13a330b159211bddb1eb70f1f02e0c0bda7c93be;hb=bb8c45f12eeaeb36ac69991f674d1971d2dc460d;hp=1d184781495c3a94db14546d3a9f3c6f9ee8e775;hpb=d3d3681f3468c633bc93a727a35bc07348245440;p=riscv-isa-sim.git

diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index 1d18478..13a330b 100644
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -8,7 +8,7 @@
 #include "debug_rom/debug_rom.h"
 #include "debug_rom/debug_rom_defines.h"
 
-#if 0
+#if 1
 #  define D(x) x
 #else
 #  define D(x)
@@ -16,13 +16,18 @@
 
 ///////////////////////// debug_module_t
 
-debug_module_t::debug_module_t(sim_t *sim, unsigned progbufsize) :
+debug_module_t::debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bus_master_bits) :
   progbufsize(progbufsize),
   program_buffer_bytes(4 + 4*progbufsize),
+  max_bus_master_bits(max_bus_master_bits),
   debug_progbuf_start(debug_data_start - program_buffer_bytes),
   debug_abstract_start(debug_progbuf_start - debug_abstract_size*4),
   sim(sim)
 {
+  D(fprintf(stderr, "debug_data_start=0x%x\n", debug_data_start));
+  D(fprintf(stderr, "debug_progbuf_start=0x%x\n", debug_progbuf_start));
+  D(fprintf(stderr, "debug_abstract_start=0x%x\n", debug_abstract_start));
+
   program_buffer = new uint8_t[program_buffer_bytes];
 
   memset(halted, 0, sizeof(halted));
@@ -70,12 +75,18 @@ void debug_module_t::reset()
   abstractauto = {0};
 
   sbcs = {0};
-  sbcs.version = 1;
-  sbcs.access64 = true;
-  sbcs.access32 = true;
-  sbcs.access16 = true;
-  sbcs.access8 = true;
-  sbcs.asize = sizeof(reg_t) * 8;
+  if (max_bus_master_bits > 0) {
+    sbcs.version = 1;
+    sbcs.asize = sizeof(reg_t) * 8;
+  }
+  if (max_bus_master_bits >= 64)
+    sbcs.access64 = true;
+  if (max_bus_master_bits >= 32)
+    sbcs.access32 = true;
+  if (max_bus_master_bits >= 16)
+    sbcs.access16 = true;
+  if (max_bus_master_bits >= 8)
+    sbcs.access8 = true;
 }
 
 void debug_module_t::add_device(bus_t *bus) {
@@ -233,7 +244,7 @@ unsigned debug_module_t::sb_access_bits()
 
 void debug_module_t::sb_autoincrement()
 {
-  if (!sbcs.autoincrement)
+  if (!sbcs.autoincrement || !max_bus_master_bits)
     return;
 
   uint64_t value = sbaddress[0] + sb_access_bits() / 8;
@@ -254,29 +265,19 @@ void debug_module_t::sb_autoincrement()
 void debug_module_t::sb_read()
 {
   reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0];
-  D(fprintf(stderr, "sb_read() @ 0x%lx\n", address));
   try {
-    switch (sbcs.sbaccess) {
-      case 0:
-        sbdata[0] = sim->debug_mmu->load_uint8(address);
-        break;
-      case 1:
-        sbdata[0] = sim->debug_mmu->load_uint16(address);
-        break;
-      case 2:
-        sbdata[0] = sim->debug_mmu->load_uint32(address);
-        D(fprintf(stderr, "   -> 0x%x\n", sbdata[0]));
-        break;
-      case 3:
-        {
-          uint64_t value = sim->debug_mmu->load_uint32(address);
-          sbdata[0] = value;
-          sbdata[1] = value >> 32;
-          break;
-        }
-      default:
-        sbcs.error = 3;
-        break;
+    if (sbcs.sbaccess == 0 && max_bus_master_bits >= 8) {
+      sbdata[0] = sim->debug_mmu->load_uint8(address);
+    } else if (sbcs.sbaccess == 1 && max_bus_master_bits >= 16) {
+      sbdata[0] = sim->debug_mmu->load_uint16(address);
+    } else if (sbcs.sbaccess == 2 && max_bus_master_bits >= 32) {
+      sbdata[0] = sim->debug_mmu->load_uint32(address);
+    } else if (sbcs.sbaccess == 3 && max_bus_master_bits >= 64) {
+      uint64_t value = sim->debug_mmu->load_uint32(address);
+      sbdata[0] = value;
+      sbdata[1] = value >> 32;
+    } else {
+      sbcs.error = 3;
     }
   } catch (trap_load_access_fault& t) {
     sbcs.error = 2;
@@ -287,23 +288,17 @@ void debug_module_t::sb_write()
 {
   reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0];
   D(fprintf(stderr, "sb_write() 0x%x @ 0x%lx\n", sbdata[0], address));
-  switch (sbcs.sbaccess) {
-    case 0:
-      sim->debug_mmu->store_uint8(address, sbdata[0]);
-      break;
-    case 1:
-      sim->debug_mmu->store_uint16(address, sbdata[0]);
-      break;
-    case 2:
-      sim->debug_mmu->store_uint32(address, sbdata[0]);
-      break;
-    case 3:
-      sim->debug_mmu->store_uint64(address,
-          (((uint64_t) sbdata[1]) << 32) | sbdata[0]);
-      break;
-    default:
-      sbcs.error = 3;
-      break;
+  if (sbcs.sbaccess == 0 && max_bus_master_bits >= 8) {
+    sim->debug_mmu->store_uint8(address, sbdata[0]);
+  } else if (sbcs.sbaccess == 1 && max_bus_master_bits >= 16) {
+    sim->debug_mmu->store_uint16(address, sbdata[0]);
+  } else if (sbcs.sbaccess == 2 && max_bus_master_bits >= 32) {
+    sim->debug_mmu->store_uint32(address, sbdata[0]);
+  } else if (sbcs.sbaccess == 3 && max_bus_master_bits >= 64) {
+    sim->debug_mmu->store_uint64(address,
+        (((uint64_t) sbdata[1]) << 32) | sbdata[0]);
+  } else {
+    sbcs.error = 3;
   }
 }
 
@@ -487,6 +482,8 @@ bool debug_module_t::perform_abstract_command()
     return true;
   }
 
+  D(fprintf(stderr, ">>> perform_abstract_command(0x%x)\n", command));
+
   if ((command >> 24) == 0) {
     // register access
     unsigned size = get_field(command, AC_ACCESS_REGISTER_SIZE);
@@ -500,49 +497,39 @@ bool debug_module_t::perform_abstract_command()
 
     if (get_field(command, AC_ACCESS_REGISTER_TRANSFER)) {
 
-      if (regno < 0x1000 || regno >= 0x1020) {
-        abstractcs.cmderr = CMDERR_NOTSUP;
-        return true;
-      }
-
-      unsigned regnum = regno - 0x1000;
+      if (regno >= 0x1000 && regno < 0x1020) {
+        unsigned regnum = regno - 0x1000;
+
+        switch (size) {
+          case 2:
+            if (write)
+              write32(debug_abstract, 0, lw(regnum, ZERO, debug_data_start));
+            else
+              write32(debug_abstract, 0, sw(regnum, ZERO, debug_data_start));
+            break;
+          case 3:
+            if (write)
+              write32(debug_abstract, 0, ld(regnum, ZERO, debug_data_start));
+            else
+              write32(debug_abstract, 0, sd(regnum, ZERO, debug_data_start));
+            break;
+          default:
+            abstractcs.cmderr = CMDERR_NOTSUP;
+            return true;
+        }
 
-      switch (size) {
-      case 2:
-        if (write)
-          write32(debug_abstract, 0, lw(regnum, ZERO, debug_data_start));
-        else
-          write32(debug_abstract, 0, sw(regnum, ZERO, debug_data_start));
-        break;
-      case 3:
-        if (write)
-          write32(debug_abstract, 0, ld(regnum, ZERO, debug_data_start));
-        else
-          write32(debug_abstract, 0, sd(regnum, ZERO, debug_data_start));
-        break;
-        /*
-          case 4:
-          if (write)
-          write32(debug_rom_code, 0, lq(regnum, ZERO, debug_data_start));
-          else
-          write32(debug_rom_code, 0, sq(regnum, ZERO, debug_data_start));
-          break;
-        */
-      default:
+      } else {
         abstractcs.cmderr = CMDERR_NOTSUP;
         return true;
       }
-    } else {
-      //NOP
-      write32(debug_abstract, 0, addi(ZERO, ZERO, 0));
-    }
 
-    if (get_field(command, AC_ACCESS_REGISTER_POSTEXEC)) {
-      // Since the next instruction is what we will use, just use nother NOP
-      // to get there.
-      write32(debug_abstract, 1, addi(ZERO, ZERO, 0));
-    } else {
-      write32(debug_abstract, 1, ebreak());
+      if (get_field(command, AC_ACCESS_REGISTER_POSTEXEC)) {
+        D(fprintf(stderr, ">>> post-exec!\n"));
+        write32(debug_abstract, 1,
+            jal(ZERO, debug_progbuf_start - debug_abstract_start - 4));
+      } else {
+        write32(debug_abstract, 1, ebreak());
+      }
     }
 
     debug_rom_flags[dmcontrol.hartsel] |= 1 << DEBUG_ROM_FLAG_GO;