X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fdebug_module.cc;h=318ef9692bf38c5cc67c3466b58aff39a0af1a0e;hb=94277648d5a0bb0e8283bbb33e25f6faab11c0d6;hp=8bcc60eada8d9eb5fbbdd8833e2463a16ae72c09;hpb=1f65ba49ea665ceed2774a1a62ac32076e4d3025;p=riscv-isa-sim.git

diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index 8bcc60e..318ef96 100644
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -5,6 +5,12 @@
 
 #include "debug_rom/debug_rom.h"
 
+#if 1
+#  define D(x) x
+#else
+#  define D(x)
+#endif
+
 bool debug_module_t::load(reg_t addr, size_t len, uint8_t* bytes)
 {
   addr = DEBUG_START + addr;
@@ -72,3 +78,14 @@ uint32_t debug_module_t::ram_read32(unsigned int index)
     (((uint32_t) base[3]) << 24);
   return value;
 }
+
+uint32_t debug_module_t::dmi_read(unsigned address)
+{
+  D(fprintf(stderr, "dmi_read(0x%x)\n", address));
+  return 0xfeed;
+}
+
+void debug_module_t::dmi_write(unsigned address, uint32_t value)
+{
+  D(fprintf(stderr, "dmi_write(0x%x, 0x%x)\n", address, value));
+}