X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fdebug_module.cc;h=f10c866ed26e21cec0f949b82712929bce898eef;hb=aa8cbb1ccd3856fd5e0437b0e24cfd7a3b794b8e;hp=2bc480a9ba6023a0098665cbbda6c974968d11fa;hpb=cd1e73b4eda7ec555f2cb832fe98d618c377ea65;p=riscv-isa-sim.git diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index 2bc480a..f10c866 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -16,9 +16,12 @@ ///////////////////////// debug_module_t -debug_module_t::debug_module_t(sim_t *sim, unsigned progbufsize) : +debug_module_t::debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bus_master_bits, + bool require_authentication) : progbufsize(progbufsize), program_buffer_bytes(4 + 4*progbufsize), + max_bus_master_bits(max_bus_master_bits), + require_authentication(require_authentication), debug_progbuf_start(debug_data_start - program_buffer_bytes), debug_abstract_start(debug_progbuf_start - debug_abstract_size*4), sim(sim) @@ -60,7 +63,7 @@ void debug_module_t::reset() dmstatus = {0}; dmstatus.impebreak = true; - dmstatus.authenticated = 1; + dmstatus.authenticated = !require_authentication; dmstatus.version = 2; abstractcs = {0}; @@ -70,12 +73,20 @@ void debug_module_t::reset() abstractauto = {0}; sbcs = {0}; - sbcs.version = 1; - sbcs.access64 = true; - sbcs.access32 = true; - sbcs.access16 = true; - sbcs.access8 = true; - sbcs.asize = sizeof(reg_t) * 8; + if (max_bus_master_bits > 0) { + sbcs.version = 1; + sbcs.asize = sizeof(reg_t) * 8; + } + if (max_bus_master_bits >= 64) + sbcs.access64 = true; + if (max_bus_master_bits >= 32) + sbcs.access32 = true; + if (max_bus_master_bits >= 16) + sbcs.access16 = true; + if (max_bus_master_bits >= 8) + sbcs.access8 = true; + + challenge = random(); } void debug_module_t::add_device(bus_t *bus) { @@ -233,7 +244,7 @@ unsigned debug_module_t::sb_access_bits() void debug_module_t::sb_autoincrement() { - if (!sbcs.autoincrement) + if (!sbcs.autoincrement || !max_bus_master_bits) return; uint64_t value = sbaddress[0] + sb_access_bits() / 8; @@ -254,29 +265,19 @@ void debug_module_t::sb_autoincrement() void debug_module_t::sb_read() { reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0]; - D(fprintf(stderr, "sb_read() @ 0x%lx\n", address)); try { - switch (sbcs.sbaccess) { - case 0: - sbdata[0] = sim->debug_mmu->load_uint8(address); - break; - case 1: - sbdata[0] = sim->debug_mmu->load_uint16(address); - break; - case 2: - sbdata[0] = sim->debug_mmu->load_uint32(address); - D(fprintf(stderr, " -> 0x%x\n", sbdata[0])); - break; - case 3: - { - uint64_t value = sim->debug_mmu->load_uint32(address); - sbdata[0] = value; - sbdata[1] = value >> 32; - break; - } - default: - sbcs.error = 3; - break; + if (sbcs.sbaccess == 0 && max_bus_master_bits >= 8) { + sbdata[0] = sim->debug_mmu->load_uint8(address); + } else if (sbcs.sbaccess == 1 && max_bus_master_bits >= 16) { + sbdata[0] = sim->debug_mmu->load_uint16(address); + } else if (sbcs.sbaccess == 2 && max_bus_master_bits >= 32) { + sbdata[0] = sim->debug_mmu->load_uint32(address); + } else if (sbcs.sbaccess == 3 && max_bus_master_bits >= 64) { + uint64_t value = sim->debug_mmu->load_uint32(address); + sbdata[0] = value; + sbdata[1] = value >> 32; + } else { + sbcs.error = 3; } } catch (trap_load_access_fault& t) { sbcs.error = 2; @@ -287,23 +288,17 @@ void debug_module_t::sb_write() { reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0]; D(fprintf(stderr, "sb_write() 0x%x @ 0x%lx\n", sbdata[0], address)); - switch (sbcs.sbaccess) { - case 0: - sim->debug_mmu->store_uint8(address, sbdata[0]); - break; - case 1: - sim->debug_mmu->store_uint16(address, sbdata[0]); - break; - case 2: - sim->debug_mmu->store_uint32(address, sbdata[0]); - break; - case 3: - sim->debug_mmu->store_uint64(address, - (((uint64_t) sbdata[1]) << 32) | sbdata[0]); - break; - default: - sbcs.error = 3; - break; + if (sbcs.sbaccess == 0 && max_bus_master_bits >= 8) { + sim->debug_mmu->store_uint8(address, sbdata[0]); + } else if (sbcs.sbaccess == 1 && max_bus_master_bits >= 16) { + sim->debug_mmu->store_uint16(address, sbdata[0]); + } else if (sbcs.sbaccess == 2 && max_bus_master_bits >= 32) { + sim->debug_mmu->store_uint32(address, sbdata[0]); + } else if (sbcs.sbaccess == 3 && max_bus_master_bits >= 64) { + sim->debug_mmu->store_uint64(address, + (((uint64_t) sbdata[1]) << 32) | sbdata[0]); + } else { + sbcs.error = 3; } } @@ -347,7 +342,8 @@ bool debug_module_t::dmi_read(unsigned address, uint32_t *value) result = set_field(result, DMI_DMCONTROL_HALTREQ, dmcontrol.haltreq); result = set_field(result, DMI_DMCONTROL_RESUMEREQ, dmcontrol.resumereq); - result = set_field(result, DMI_DMCONTROL_HARTSEL, dmcontrol.hartsel); + result = set_field(result, ((1L<= DMI_DATA0 && address < DMI_DATA0 + abstractcs.datacount) { unsigned i = address - DMI_DATA0; if (!abstractcs.busy) @@ -588,12 +592,15 @@ bool debug_module_t::dmi_write(unsigned address, uint32_t value) if (!dmcontrol.dmactive && get_field(value, DMI_DMCONTROL_DMACTIVE)) reset(); dmcontrol.dmactive = get_field(value, DMI_DMCONTROL_DMACTIVE); + if (!dmstatus.authenticated) + return true; if (dmcontrol.dmactive) { dmcontrol.haltreq = get_field(value, DMI_DMCONTROL_HALTREQ); dmcontrol.resumereq = get_field(value, DMI_DMCONTROL_RESUMEREQ); dmcontrol.hartreset = get_field(value, DMI_DMCONTROL_HARTRESET); dmcontrol.ndmreset = get_field(value, DMI_DMCONTROL_NDMRESET); - dmcontrol.hartsel = get_field(value, DMI_DMCONTROL_HARTSEL); + dmcontrol.hartsel = get_field(value, ((1L<