X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fdebug_module.h;h=82c449ef6a70a699af5438db8a9adc83e353a356;hb=bb8c45f12eeaeb36ac69991f674d1971d2dc460d;hp=ca3ff312600ce00b434f776dba420562bea0b3b3;hpb=773fab34d46e2ddaf4318b851ab23bd813f168ad;p=riscv-isa-sim.git diff --git a/riscv/debug_module.h b/riscv/debug_module.h index ca3ff31..82c449e 100644 --- a/riscv/debug_module.h +++ b/riscv/debug_module.h @@ -18,6 +18,7 @@ typedef struct { } dmcontrol_t; typedef struct { + bool impebreak; bool allnonexistant; bool anynonexistant; bool allunavail; @@ -26,25 +27,28 @@ typedef struct { bool anyrunning; bool allhalted; bool anyhalted; + bool allresumeack; + bool anyresumeack; bool authenticated; bool authbusy; bool cfgstrvalid; - unsigned versionhi; - unsigned versionlo; + unsigned version; } dmstatus_t; -typedef struct { - bool busy; - unsigned datacount; - unsigned progsize; - enum { +typedef enum cmderr { CMDERR_NONE = 0, CMDERR_BUSY = 1, CMDERR_NOTSUP = 2, CMDERR_EXCEPTION = 3, CMDERR_HALTRESUME = 4, - CMDERR_OTHER = 7 - } cmderr; + CMDERR_OTHER = 7 +} cmderr_t; + +typedef struct { + bool busy; + unsigned datacount; + unsigned progbufsize; + cmderr_t cmderr; } abstractcs_t; typedef struct { @@ -52,24 +56,26 @@ typedef struct { unsigned autoexecdata; } abstractauto_t; -class debug_module_data_t : public abstract_device_t -{ - public: - debug_module_data_t(); - - bool load(reg_t addr, size_t len, uint8_t* bytes); - bool store(reg_t addr, size_t len, const uint8_t* bytes); - - uint32_t read32(reg_t addr) const; - void write32(reg_t addr, uint32_t value); - - uint8_t data[DEBUG_EXCHANGE_SIZE]; -}; +typedef struct { + unsigned version; + bool readonaddr; + unsigned sbaccess; + bool autoincrement; + bool readondata; + unsigned error; + unsigned asize; + bool access128; + bool access64; + bool access32; + bool access16; + bool access8; +} sbcs_t; class debug_module_t : public abstract_device_t { public: - debug_module_t(sim_t *sim); + debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bus_master_bits); + ~debug_module_t(); void add_device(bus_t *bus); @@ -83,30 +89,51 @@ class debug_module_t : public abstract_device_t bool dmi_write(unsigned address, uint32_t value); private: - static const unsigned progsize = 8; + static const unsigned datasize = 2; + // Size of program_buffer in 32-bit words, as exposed to the rest of the + // world. + unsigned progbufsize; + // Actual size of the program buffer, which is 1 word bigger than we let on + // to implement the implicit ebreak at the end. + unsigned program_buffer_bytes; + unsigned max_bus_master_bits ; + static const unsigned debug_data_start = 0x380; + unsigned debug_progbuf_start; + + static const unsigned debug_abstract_size = 5; + unsigned debug_abstract_start; + + static const unsigned hartsellen = 10; sim_t *sim; - uint8_t debug_rom_entry[DEBUG_ROM_ENTRY_SIZE]; - uint8_t debug_rom_code[DEBUG_ROM_CODE_SIZE]; - uint8_t debug_rom_exception[DEBUG_ROM_EXCEPTION_SIZE]; - uint8_t program_buffer[progsize * 4]; + uint8_t debug_rom_whereto[4]; + uint8_t debug_abstract[debug_abstract_size * 4]; + uint8_t *program_buffer; + uint8_t dmdata[datasize * 4]; + bool halted[1024]; - debug_module_data_t dmdata; - // Instruction that will be placed at the current hart's ROM entry address - // after the current action has completed. - uint32_t next_action; - bool action_executed; + bool resumeack[1024]; + uint8_t debug_rom_flags[1024]; void write32(uint8_t *rom, unsigned int index, uint32_t value); uint32_t read32(uint8_t *rom, unsigned int index); + void sb_autoincrement(); + void sb_read(); + void sb_write(); + unsigned sb_access_bits(); + dmcontrol_t dmcontrol; dmstatus_t dmstatus; abstractcs_t abstractcs; abstractauto_t abstractauto; uint32_t command; + sbcs_t sbcs; + uint32_t sbaddress[4]; + uint32_t sbdata[4]; + processor_t *current_proc() const; void reset(); bool perform_abstract_command();