X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fdebug_module.h;h=d581be8338c5d0e23a26c758b240061bd85d0570;hb=d3d3681f3468c633bc93a727a35bc07348245440;hp=00c66cc72253916c36366601ebfd2e40017fd92f;hpb=3582bab41908a649c975ae98ad97a0d84b48dcde;p=riscv-isa-sim.git

diff --git a/riscv/debug_module.h b/riscv/debug_module.h
index 00c66cc..d581be8 100644
--- a/riscv/debug_module.h
+++ b/riscv/debug_module.h
@@ -56,6 +56,21 @@ typedef struct {
   unsigned autoexecdata;
 } abstractauto_t;
 
+typedef struct {
+  unsigned version;
+  bool readonaddr;
+  unsigned sbaccess;
+  bool autoincrement;
+  bool readondata;
+  unsigned error;
+  unsigned asize;
+  bool access128;
+  bool access64;
+  bool access32;
+  bool access16;
+  bool access8;
+} sbcs_t;
+
 class debug_module_t : public abstract_device_t
 {
   public:
@@ -87,6 +102,8 @@ class debug_module_t : public abstract_device_t
     static const unsigned debug_abstract_size = 2;
     unsigned debug_abstract_start;
 
+    static const unsigned hartsellen = 10;
+
     sim_t *sim;
 
     uint8_t debug_rom_whereto[4];
@@ -101,12 +118,21 @@ class debug_module_t : public abstract_device_t
     void write32(uint8_t *rom, unsigned int index, uint32_t value);
     uint32_t read32(uint8_t *rom, unsigned int index);
 
+    void sb_autoincrement();
+    void sb_read();
+    void sb_write();
+    unsigned sb_access_bits();
+
     dmcontrol_t dmcontrol;
     dmstatus_t dmstatus;
     abstractcs_t abstractcs;
     abstractauto_t abstractauto;
     uint32_t command;
 
+    sbcs_t sbcs;
+    uint32_t sbaddress[4];
+    uint32_t sbdata[4];
+
     processor_t *current_proc() const;
     void reset();
     bool perform_abstract_command();