X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fdebug_module.h;h=e554ffc8f3623863851a1a4f5fbf4192402fae69;hb=aa8cbb1ccd3856fd5e0437b0e24cfd7a3b794b8e;hp=8daf03b58caa9b783da3a45382db5e74944cbbaa;hpb=12b772563a33b6c6c3da0343fbfc747b1eeea6b6;p=riscv-isa-sim.git

diff --git a/riscv/debug_module.h b/riscv/debug_module.h
index 8daf03b..e554ffc 100644
--- a/riscv/debug_module.h
+++ b/riscv/debug_module.h
@@ -18,6 +18,7 @@ typedef struct {
 } dmcontrol_t;
 
 typedef struct {
+  bool impebreak;
   bool allnonexistant;
   bool anynonexistant;
   bool allunavail;
@@ -31,8 +32,7 @@ typedef struct {
   bool authenticated;
   bool authbusy;
   bool cfgstrvalid;
-  unsigned versionhi;
-  unsigned versionlo;
+  unsigned version;
 } dmstatus_t;
 
 typedef enum cmderr {
@@ -47,7 +47,7 @@ typedef enum cmderr {
 typedef struct {
   bool busy;
   unsigned datacount;
-  unsigned progsize;
+  unsigned progbufsize;
   cmderr_t cmderr;
 } abstractcs_t;
 
@@ -56,10 +56,33 @@ typedef struct {
   unsigned autoexecdata;
 } abstractauto_t;
 
+typedef struct {
+  unsigned version;
+  bool readonaddr;
+  unsigned sbaccess;
+  bool autoincrement;
+  bool readondata;
+  unsigned error;
+  unsigned asize;
+  bool access128;
+  bool access64;
+  bool access32;
+  bool access16;
+  bool access8;
+} sbcs_t;
+
 class debug_module_t : public abstract_device_t
 {
   public:
-    debug_module_t(sim_t *sim);
+    /*
+     * If require_authentication is true, then a debugger must authenticate as
+     * follows:
+     * 1. Read a 32-bit value from authdata:
+     * 2. Write the value that was read back, plus one, to authdata.
+     */
+    debug_module_t(sim_t *sim, unsigned progbufsize, unsigned max_bus_master_bits,
+        bool require_authentication);
+    ~debug_module_t();
 
     void add_device(bus_t *bus);
 
@@ -73,33 +96,55 @@ class debug_module_t : public abstract_device_t
     bool dmi_write(unsigned address, uint32_t value);
 
   private:
-    static const unsigned progsize = 8;
+    static const unsigned datasize = 2;
+    // Size of program_buffer in 32-bit words, as exposed to the rest of the
+    // world.
+    unsigned progbufsize;
+    // Actual size of the program buffer, which is 1 word bigger than we let on
+    // to implement the implicit ebreak at the end.
+    unsigned program_buffer_bytes;
+    unsigned max_bus_master_bits;
+    bool require_authentication;
+    static const unsigned debug_data_start = 0x380;
+    unsigned debug_progbuf_start;
+
+    static const unsigned debug_abstract_size = 2;
+    unsigned debug_abstract_start;
+
+    static const unsigned hartsellen = 10;
 
     sim_t *sim;
 
-    uint8_t debug_rom_entry[DEBUG_ROM_ENTRY_SIZE];
-    uint8_t debug_rom_code[DEBUG_ROM_CODE_SIZE];
-    uint8_t debug_rom_exception[DEBUG_ROM_EXCEPTION_SIZE];
-    uint8_t program_buffer[progsize * 4];
-    uint8_t dmdata[DEBUG_DATA_SIZE];
+    uint8_t debug_rom_whereto[4];
+    uint8_t debug_abstract[debug_abstract_size * 4];
+    uint8_t *program_buffer;
+    uint8_t dmdata[datasize * 4];
     
     bool halted[1024];
     bool resumeack[1024];
-
-    // Instruction that will be placed at the current hart's ROM entry address
-    // after the current action has completed.
-    uint32_t next_action;
-    bool action_executed;
+    uint8_t debug_rom_flags[1024];
 
     void write32(uint8_t *rom, unsigned int index, uint32_t value);
     uint32_t read32(uint8_t *rom, unsigned int index);
 
+    void sb_autoincrement();
+    void sb_read();
+    void sb_write();
+    unsigned sb_access_bits();
+
     dmcontrol_t dmcontrol;
     dmstatus_t dmstatus;
     abstractcs_t abstractcs;
     abstractauto_t abstractauto;
     uint32_t command;
 
+    sbcs_t sbcs;
+    uint32_t sbaddress[4];
+    uint32_t sbdata[4];
+
+    uint32_t challenge;
+    const uint32_t secret = 1;
+
     processor_t *current_proc() const;
     void reset();
     bool perform_abstract_command();