X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fdecode.h;h=596a2ad9bfea1bfe24b38ed1b733e5a8c91bb688;hb=4299874ad4b07ef457776513a64e5b2397a6a75e;hp=a1c28d50827d6a0a0a888c84595bc4dff77a6ad8;hpb=7f3c072750a71f2800cfb03531ec16699c20bb34;p=riscv-isa-sim.git diff --git a/riscv/decode.h b/riscv/decode.h index a1c28d5..596a2ad 100644 --- a/riscv/decode.h +++ b/riscv/decode.h @@ -7,20 +7,29 @@ # error spike requires a two''s-complement c++ implementation #endif +#ifdef WORDS_BIGENDIAN +# error spike requires a little-endian host +#endif + #include #include #include #include "encoding.h" #include "config.h" #include "common.h" +#include "softfloat_types.h" +#include "specialize.h" #include typedef int64_t sreg_t; typedef uint64_t reg_t; -typedef uint64_t freg_t; const int NXPR = 32; const int NFPR = 32; +const int NCSR = 4096; + +#define X_RA 1 +#define X_SP 2 #define FP_RD_NE 0 #define FP_RD_0 1 @@ -45,19 +54,13 @@ const int NFPR = 32; #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) -#ifdef RISCV_ENABLE_RVC -# define INSN_ALIGNMENT 2 -# define require_rvc -#else -# define INSN_ALIGNMENT 4 -# define require_rvc throw trap_illegal_instruction() -#endif - #define insn_length(x) \ (((x) & 0x03) < 0x03 ? 2 : \ ((x) & 0x1f) < 0x1f ? 4 : \ ((x) & 0x3f) < 0x3f ? 6 : \ 8) +#define MAX_INSN_LENGTH 8 +#define PC_ALIGN 2 typedef uint64_t insn_bits_t; class insn_t @@ -80,18 +83,23 @@ public: uint64_t csr() { return x(20, 12); } int64_t rvc_imm() { return x(2, 5) + (xs(12, 1) << 5); } + int64_t rvc_zimm() { return x(2, 5) + (x(12, 1) << 5); } + int64_t rvc_addi4spn_imm() { return (x(6, 1) << 2) + (x(5, 1) << 3) + (x(11, 2) << 4) + (x(7, 4) << 6); } + int64_t rvc_addi16sp_imm() { return (x(6, 1) << 4) + (x(2, 1) << 5) + (x(5, 1) << 6) + (x(3, 2) << 7) + (xs(12, 1) << 9); } int64_t rvc_lwsp_imm() { return (x(4, 3) << 2) + (x(12, 1) << 5) + (x(2, 2) << 6); } int64_t rvc_ldsp_imm() { return (x(5, 2) << 3) + (x(12, 1) << 5) + (x(2, 3) << 6); } - int64_t rvc_lw_imm() { return (x(5, 2) << 3) + (x(10, 1) << 6) + (x(11, 1) << 2) + (x(12, 1) << 5); } - int64_t rvc_ld_imm() { return (x(5, 2) << 3) + (x(10, 1) << 6) + (x(11, 1) << 7) + (x(12, 1) << 5); } - int64_t rvc_j_imm() { return (xs(2, 3) << 9) + (x(5, 2) << 3) + (x(7, 1) << 1) + (x(8, 2) << 7) + (x(10, 1) << 6) + (x(11, 1) << 2) + (x(12, 1) << 5); } - int64_t rvc_b_imm() { return (x(5, 2) << 3) + (x(7, 1) << 1) + (xs(8, 2) << 7) + (x(10, 1) << 6) + (x(11, 1) << 2) + (x(12, 1) << 5); } + int64_t rvc_swsp_imm() { return (x(9, 4) << 2) + (x(7, 2) << 6); } + int64_t rvc_sdsp_imm() { return (x(10, 3) << 3) + (x(7, 3) << 6); } + int64_t rvc_lw_imm() { return (x(6, 1) << 2) + (x(10, 3) << 3) + (x(5, 1) << 6); } + int64_t rvc_ld_imm() { return (x(10, 3) << 3) + (x(5, 2) << 6); } + int64_t rvc_j_imm() { return (x(3, 3) << 1) + (x(11, 1) << 4) + (x(2, 1) << 5) + (x(7, 1) << 6) + (x(6, 1) << 7) + (x(9, 2) << 8) + (x(8, 1) << 10) + (xs(12, 1) << 11); } + int64_t rvc_b_imm() { return (x(3, 2) << 1) + (x(10, 2) << 3) + (x(2, 1) << 5) + (x(5, 2) << 6) + (xs(12, 1) << 8); } + int64_t rvc_simm3() { return x(10, 3); } uint64_t rvc_rd() { return rd(); } - uint64_t rvc_rs1() { return x(2, 5); } - uint64_t rvc_rs2() { return rd(); } - uint64_t rvc_rds() { return 8 + x(7, 3); } - uint64_t rvc_rs1s() { return 8 + x(2, 3); } - uint64_t rvc_rs2s() { return rvc_rds(); } + uint64_t rvc_rs1() { return rd(); } + uint64_t rvc_rs2() { return x(2, 5); } + uint64_t rvc_rs1s() { return 8 + x(7, 3); } + uint64_t rvc_rs2s() { return 8 + x(2, 3); } private: insn_bits_t b; uint64_t x(int lo, int len) { return (b >> lo) & ((insn_bits_t(1) << len)-1); } @@ -119,65 +127,72 @@ private: // helpful macros, etc #define MMU (*p->get_mmu()) #define STATE (*p->get_state()) -#define RS1 STATE.XPR[insn.rs1()] -#define RS2 STATE.XPR[insn.rs2()] -#define WRITE_REG(reg, value) STATE.XPR.write(reg, value) +#define READ_REG(reg) STATE.XPR[reg] +#define READ_FREG(reg) STATE.FPR[reg] +#define RS1 READ_REG(insn.rs1()) +#define RS2 READ_REG(insn.rs2()) #define WRITE_RD(value) WRITE_REG(insn.rd(), value) -#ifdef RISCV_ENABLE_COMMITLOG - #undef WRITE_REG - #define WRITE_REG(reg, value) ({ \ - reg_t wdata = value; /* value is a func with side-effects */ \ - STATE.log_reg_write = (commit_log_reg_t){reg << 1, wdata}; \ - STATE.XPR.write(reg, wdata); \ - }) +#ifndef RISCV_ENABLE_COMMITLOG +# define WRITE_REG(reg, value) STATE.XPR.write(reg, value) +# define WRITE_FREG(reg, value) DO_WRITE_FREG(reg, freg(value)) +#else +# define WRITE_REG(reg, value) ({ \ + reg_t wdata = (value); /* value may have side effects */ \ + STATE.log_reg_write = (commit_log_reg_t){(reg) << 1, {wdata, 0}}; \ + STATE.XPR.write(reg, wdata); \ + }) +# define WRITE_FREG(reg, value) ({ \ + freg_t wdata = freg(value); /* value may have side effects */ \ + STATE.log_reg_write = (commit_log_reg_t){((reg) << 1) | 1, wdata}; \ + DO_WRITE_FREG(reg, wdata); \ + }) #endif // RVC macros -#define WRITE_RVC_RDS(value) WRITE_REG(insn.rvc_rds(), value) -#define RVC_RS1 STATE.XPR[insn.rvc_rs1()] -#define RVC_RS2 STATE.XPR[insn.rvc_rs2()] -#define RVC_RS1S STATE.XPR[insn.rvc_rs1s()] -#define RVC_RS2S STATE.XPR[insn.rvc_rs2s()] -#define RVC_SP STATE.XPR[2] +#define WRITE_RVC_RS1S(value) WRITE_REG(insn.rvc_rs1s(), value) +#define WRITE_RVC_RS2S(value) WRITE_REG(insn.rvc_rs2s(), value) +#define WRITE_RVC_FRS2S(value) WRITE_FREG(insn.rvc_rs2s(), value) +#define RVC_RS1 READ_REG(insn.rvc_rs1()) +#define RVC_RS2 READ_REG(insn.rvc_rs2()) +#define RVC_RS1S READ_REG(insn.rvc_rs1s()) +#define RVC_RS2S READ_REG(insn.rvc_rs2s()) +#define RVC_FRS2 READ_FREG(insn.rvc_rs2()) +#define RVC_FRS2S READ_FREG(insn.rvc_rs2s()) +#define RVC_SP READ_REG(X_SP) // FPU macros -#define FRS1 STATE.FPR[insn.rs1()] -#define FRS2 STATE.FPR[insn.rs2()] -#define FRS3 STATE.FPR[insn.rs3()] +#define FRS1 READ_FREG(insn.rs1()) +#define FRS2 READ_FREG(insn.rs2()) +#define FRS3 READ_FREG(insn.rs3()) #define dirty_fp_state (STATE.mstatus |= MSTATUS_FS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD)) #define dirty_ext_state (STATE.mstatus |= MSTATUS_XS | (xlen == 64 ? MSTATUS64_SD : MSTATUS32_SD)) -#define do_write_frd(value) (STATE.FPR.write(insn.rd(), value), dirty_fp_state) - -#ifndef RISCV_ENABLE_COMMITLOG -# define WRITE_FRD(value) do_write_frd(value) -#else -# define WRITE_FRD(value) ({ \ - freg_t wdata = (value); /* value may have side effects */ \ - STATE.log_reg_write = (commit_log_reg_t){(insn.rd() << 1) | 1, wdata}; \ - do_write_frd(wdata); \ - }) -#endif +#define DO_WRITE_FREG(reg, value) (STATE.FPR.write(reg, value), dirty_fp_state) +#define WRITE_FRD(value) WRITE_FREG(insn.rd(), value) #define SHAMT (insn.i_imm() & 0x3F) #define BRANCH_TARGET (pc + insn.sb_imm()) #define JUMP_TARGET (pc + insn.uj_imm()) #define RM ({ int rm = insn.rm(); \ if(rm == 7) rm = STATE.frm; \ - if(rm > 4) throw trap_illegal_instruction(); \ + if(rm > 4) throw trap_illegal_instruction(0); \ rm; }) #define get_field(reg, mask) (((reg) & (decltype(reg))(mask)) / ((mask) & ~((mask) << 1))) #define set_field(reg, mask, val) (((reg) & ~(decltype(reg))(mask)) | (((decltype(reg))(val) * ((mask) & ~((mask) << 1))) & (decltype(reg))(mask))) -#define require_privilege(p) if (get_field(STATE.mstatus, MSTATUS_PRV) < (p)) throw trap_illegal_instruction() -#define require_rv64 if(unlikely(xlen != 64)) throw trap_illegal_instruction() -#define require_rv32 if(unlikely(xlen != 32)) throw trap_illegal_instruction() -#define require_fp if (unlikely((STATE.mstatus & MSTATUS_FS) == 0)) throw trap_illegal_instruction() -#define require_accelerator if (unlikely((STATE.mstatus & MSTATUS_XS) == 0)) throw trap_illegal_instruction() +#define require(x) if (unlikely(!(x))) throw trap_illegal_instruction(0) +#define require_privilege(p) require(STATE.prv >= (p)) +#define require_rv64 require(xlen == 64) +#define require_rv32 require(xlen == 32) +#define require_extension(s) require(p->supports_extension(s)) +#define require_fp require((STATE.mstatus & MSTATUS_FS) != 0) +#define require_accelerator require((STATE.mstatus & MSTATUS_XS) != 0) -#define cmp_trunc(reg) (reg_t(reg) << (64-xlen)) -#define set_fp_exceptions ({ STATE.fflags |= softfloat_exceptionFlags; \ +#define set_fp_exceptions ({ if (softfloat_exceptionFlags) { \ + dirty_fp_state; \ + STATE.fflags |= softfloat_exceptionFlags; \ + } \ softfloat_exceptionFlags = 0; }) #define sext32(x) ((sreg_t)(int32_t)(x)) @@ -186,21 +201,74 @@ private: #define zext_xlen(x) (((reg_t)(x) << (64-xlen)) >> (64-xlen)) #define set_pc(x) \ - do { if ((x) & (INSN_ALIGNMENT-1)) \ - throw trap_instruction_address_misaligned(x); \ + do { p->check_pc_alignment(x); \ npc = sext_xlen(x); \ } while(0) -#define PC_SERIALIZE 3 /* sentinel value indicating simulator pipeline flush */ +#define set_pc_and_serialize(x) \ + do { reg_t __npc = (x); \ + npc = PC_SERIALIZE_AFTER; \ + STATE.pc = __npc; \ + } while(0) + +#define serialize() set_pc_and_serialize(npc) + +/* Sentinel PC values to serialize simulator pipeline */ +#define PC_SERIALIZE_BEFORE 3 +#define PC_SERIALIZE_AFTER 5 +#define invalid_pc(pc) ((pc) & 1) + +/* Convenience wrappers to simplify softfloat code sequences */ +#define isBoxedF32(r) (isBoxedF64(r) && ((uint32_t)((r.v[0] >> 32) + 1) == 0)) +#define unboxF32(r) (isBoxedF32(r) ? (uint32_t)r.v[0] : defaultNaNF32UI) +#define isBoxedF64(r) ((r.v[1] + 1) == 0) +#define unboxF64(r) (isBoxedF64(r) ? r.v[0] : defaultNaNF64UI) +typedef float128_t freg_t; +inline float32_t f32(uint32_t v) { return { v }; } +inline float64_t f64(uint64_t v) { return { v }; } +inline float32_t f32(freg_t r) { return f32(unboxF32(r)); } +inline float64_t f64(freg_t r) { return f64(unboxF64(r)); } +inline float128_t f128(freg_t r) { return r; } +inline freg_t freg(float32_t f) { return { ((uint64_t)-1 << 32) | f.v, (uint64_t)-1 }; } +inline freg_t freg(float64_t f) { return { f.v, (uint64_t)-1 }; } +inline freg_t freg(float128_t f) { return f; } +#define F32_SIGN ((uint32_t)1 << 31) +#define F64_SIGN ((uint64_t)1 << 63) +#define fsgnj32(a, b, n, x) \ + f32((f32(a).v & ~F32_SIGN) | ((((x) ? f32(a).v : (n) ? F32_SIGN : 0) ^ f32(b).v) & F32_SIGN)) +#define fsgnj64(a, b, n, x) \ + f64((f64(a).v & ~F64_SIGN) | ((((x) ? f64(a).v : (n) ? F64_SIGN : 0) ^ f64(b).v) & F64_SIGN)) + +#define isNaNF128(x) isNaNF128UI(x.v[1], x.v[0]) +inline float128_t defaultNaNF128() +{ + float128_t nan; + nan.v[1] = defaultNaNF128UI64; + nan.v[0] = defaultNaNF128UI0; + return nan; +} +inline freg_t fsgnj128(freg_t a, freg_t b, bool n, bool x) +{ + a.v[1] = (a.v[1] & ~F64_SIGN) | (((x ? a.v[1] : n ? F64_SIGN : 0) ^ b.v[1]) & F64_SIGN); + return a; +} +inline freg_t f128_negate(freg_t a) +{ + a.v[1] ^= F64_SIGN; + return a; +} #define validate_csr(which, write) ({ \ - if (!STATE.serialized) return PC_SERIALIZE; \ + if (!STATE.serialized) return PC_SERIALIZE_BEFORE; \ STATE.serialized = false; \ - unsigned my_priv = get_field(STATE.mstatus, MSTATUS_PRV); \ unsigned csr_priv = get_field((which), 0x300); \ unsigned csr_read_only = get_field((which), 0xC00) == 3; \ - if (((write) && csr_read_only) || my_priv < csr_priv) \ - throw trap_illegal_instruction(); \ + if (((write) && csr_read_only) || STATE.prv < csr_priv) \ + throw trap_illegal_instruction(0); \ (which); }) +// Seems that 0x0 doesn't work. +#define DEBUG_START 0x100 +#define DEBUG_END (0x1000 - 1) + #endif