X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fdecode.h;h=7cf7eacc913abb30d71ffbcb9d79b2a299f17ff2;hb=b9dc340b7567404c76b6a7e042c2fa3c59787515;hp=bde921f08db4a03b14c63ff8c5d4e4110603765f;hpb=c8a8c07ec296ce36dc04f2448faf48fe1c502a2d;p=riscv-isa-sim.git

diff --git a/riscv/decode.h b/riscv/decode.h
index bde921f..7cf7eac 100644
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -13,6 +13,7 @@
 #include "pcr.h"
 #include "config.h"
 #include "common.h"
+#include <cinttypes>
 
 typedef int int128_t __attribute__((mode(TI)));
 typedef unsigned int uint128_t __attribute__((mode(TI)));
@@ -96,10 +97,36 @@ private:
 #define RS1 p->get_state()->XPR[insn.rs1()]
 #define RS2 p->get_state()->XPR[insn.rs2()]
 #define WRITE_RD(value) p->get_state()->XPR.write(insn.rd(), value)
+
+#ifdef RISCV_ENABLE_COMMITLOG
+  #undef WRITE_RD 
+  #define WRITE_RD(value) ({ \
+        bool in_spvr = p->get_state()->sr & SR_S; \
+        reg_t wdata = value; /* value is a func with side-effects */ \
+        if (!in_spvr) \
+          fprintf(stderr, "x%u 0x%016" PRIx64, insn.rd(), ((uint64_t) wdata)); \
+        p->get_state()->XPR.write(insn.rd(), wdata); \
+      })
+#endif
+
 #define FRS1 p->get_state()->FPR[insn.rs1()]
 #define FRS2 p->get_state()->FPR[insn.rs2()]
 #define FRS3 p->get_state()->FPR[insn.rs3()]
 #define WRITE_FRD(value) p->get_state()->FPR.write(insn.rd(), value)
+ 
+#ifdef RISCV_ENABLE_COMMITLOG
+  #undef WRITE_FRD 
+  #define WRITE_FRD(value) ({ \
+        bool in_spvr = p->get_state()->sr & SR_S; \
+        freg_t wdata = value; /* value is a func with side-effects */ \
+        if (!in_spvr) \
+          fprintf(stderr, "f%u 0x%016" PRIx64, insn.rd(), ((uint64_t) wdata)); \
+        p->get_state()->FPR.write(insn.rd(), wdata); \
+      })
+#endif
+ 
+
+
 #define SHAMT (insn.i_imm() & 0x3F)
 #define BRANCH_TARGET (pc + insn.sb_imm())
 #define JUMP_TARGET (pc + insn.uj_imm())