X-Git-Url: https://git.libre-soc.org/?a=blobdiff_plain;f=riscv%2Fexecute.cc;h=303effee84ae4f9c3851c5ec0788683fbe007d95;hb=8fda4e00ea7326d6f2a2867c7482559bf5b0b401;hp=7734ca2749d6756ca2270e6c359a3d28db712ec9;hpb=3526283513b12afc57c3430c70190fe1630564e6;p=riscv-isa-sim.git

diff --git a/riscv/execute.cc b/riscv/execute.cc
index 7734ca2..303effe 100644
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -65,7 +65,8 @@ void processor_t::step(size_t n)
   if (state.dcsr.cause == DCSR_CAUSE_NONE) {
     if (halt_request) {
       enter_debug_mode(DCSR_CAUSE_DEBUGINT);
-    } else if (state.dcsr.halt) {
+    } // !!!The halt bit in DCSR is deprecated.
+    else if (state.dcsr.halt) {
       enter_debug_mode(DCSR_CAUSE_HALT);
     }
   }
@@ -116,12 +117,14 @@ void processor_t::step(size_t n)
             break;
           }
 
-          if (unlikely(state.pc >= DEBUG_ROM_ENTRY &&
-                state.pc < DEBUG_ROM_ENTRY + DEBUG_ROM_ENTRY_SIZE)) {
-            // We're spinning waiting for the debugger to tell us something.
-            // Let's go talk to the debugger.
+          if (unlikely(state.pc >= DEBUG_START &&
+                       state.pc < DEBUG_END)) {
+            // We're waiting for the debugger to tell us something.
             return;
           }
+
+          
+          
         }
       }
       else while (instret < n)